Fumio Ootsuka

A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications

A 130 nm node CMOS technology with a self-aligned contact system is demonstrated. Tensile stress of the contact etch stop increases nFETs Ids, and reduces compressive stress caused by shallow trench isolation, which enhances pFETs Ids. A 1.92 /spl mu/m/sup 2/ 6T-SRAM has been integrated with high performance transistors.

A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

An SRAM cell is proposed, in which additional capacitance is formed between the two local interconnects which are used for cross couple wiring. This novel cell with stacked cross couple (SCC) has an advantage in reducing the cell area to 80% of that of the conventional SRAM cell. Furthermore, the capacitor area can be enlarged to 40% of the cell area which enables one to adopt thick capacitor insulator. Reduction in capacitor leakage current by using plasma SiN with low Si-H concentration, and the device performances are also discussed.

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enriched interface (OI-SiN) to suppress both the gate-leakage current and boron penetration. Consequently, N-MOSFET and P-MOSFET have high drive currents of 0.68 and 0.30 mA//spl mu/m, respectively, with I/sub off/=10 nA//spl mu/m, with an EOT value of 1.4 nm. The record gate delay of 280 fs (3.6 THz), for an N-MOSFET with the gate length of 19 nm, has also been achieved.

Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High-

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (VTH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low VTH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of VTH roll-offs and Ion-Ioffs if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

k

The method and the results of the evaluation of the activation energy of interface state generation are presented. The energy distribution of the hot electron can be well described as Maxwellian if the effective electron temperature is low enough compared to the energy under consideration, and the activation energy can be defined by means of electron temperature. The activation energy of interface state generation is expressed as E/sub it/ n alpha E/sub imp/, where n describes the time dependence of interface state generation alpha is the ionization efficiency, and E/sub imp/ is the activation energy of impact ionization. The obtained value of E/sub it/ is 8.7 eV. This value is consistent with the model in which the breaking of the Si-H bond and hydrogen diffusion occur at the interface. This mechanism can be related to a hydrogen diffusion equation which contains interaction between hydrogen and other substances in SiO/sub 2/. Based on this diffusion equation, interface state generation can be expressed by the two terms of generation and recombination. This hydrogen diffusion model predicts the hot-carrier phenomena well enough. >

FETs

This brief presents a method to extract the equivalent oxide thickness (EOT) from the capacitance-voltage (C-V) as an asymptotic solution in strong accumulation. This method does not need the information of the flat-band voltage (V/sub FB/) or the substrate concentration, and hence, EOT is extracted irrelevant of the substrate dopant profile. This method can be applied to the real FETs in which substrate or channel dopant concentration is not uniform. In addition, the method is presented to evaluate the electron and hole mobility as a function of the channel electric field which is derived by using the EOT value extracted by this new method.

The evaluation of the activation energy of interface state generation by hot-electron injection

Apparent difference of the dielectric breakdown behavior between high-k stack and the conventional SiO2 is investigated by the temperature dependence of TDDB lifetime. It is clarified that the temperature dependence of TDDB lifetime in high-k stack can be described by two parameters, which is identical to the case of conventional SiO2.

An engineering method to extract equivalent oxide thickness and its extension to channel mobility evaluation

We have realized a 0.9nm-EOT TaSix/HfSiON gate stack that exhibits the high electron mobility of 264 cm2/Vs @ 0.8MV/cm (86% of thermal SiO2), even after spike annealing at 1000degC. This was achieved by using thermally-stable HfSiON gate dielectrics with plasma nitridation, in which interfacial layer growth due to recoiled oxygen had been successfully suppressed

Reliability Perspective of High-k Gate Stack Assessed by Temperature Dependence of Dielectric Breakdown

In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this presentation, gate stack technology using high-k gate dielectrics and metal gate will be discussed, and recent achievements of these technologies will be reviewed

A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices

This paper describes the 65nm-node HfSiON transistors that have been fully integrated to SRAM array. By optimizing the thermal process after the gate stack formation, the scaling of EOT has been attained without introducing additional high-k formation techniques. Highly manufacturable HfSiON transistors with the symmetrical Vth values suitable for SRAM operation at 1.1V power supply are demonstrated.