Masaaki Kinugawa

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/. >

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >

Reliability and performance of submicron LDD NMOSFET's with buried As n - impurity profiles

The reliability and performance of submicron LDD NMOSFETs with retrograde Arsenic impurity profiles in the n-region were investigated. These structures were compared to devices with conventional As drains and phosphorus-implanted (P+) LDDs. Reduced substrate current was expected from 2D simulation and was confirmed experimentally. Lifetime under DC stress was improved by a factor of 15 over that observed for LDD devices. Transconductance was 93% of a conventional NMOSFET and 5% greater than a LDD FET having a P+implant of4 \times 10^{13}cm-2, CMOS ring oscillator stage delay was equal to or better than the delay for LDD and conventional NMOSFETs and depicted a tradeoff between gmand gate-drain overlap capacitance Cdg. Short channel effects were evaluated for Leffdown to 0.45 µm and found to be similar to standard LDD designs.

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

A 4-Mb (512 K words by 8-b) CMOS static RAM (SRAM) with a PMOS thin-film transistor (TFT) has been developed. The RAM can obtain a much larger data-retention margin than a conventional high-resistive load-type well by using the PMOS TFT as a memory cell load. An internal voltage down-converter architecture with an external supply voltage-level sensor not only realizes a highly reliable 0.5- mu m MOS transistor operation but also a sufficiently low standby-power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a 0.5 mu m, triple-poly, and double-aluminum with dual gate-oxide-thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively. >

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<<ETX>>

Effects of silicon surface orientation on submicron CMOS devices

Effects of Si surface orientation on small dimension NMOS and PMOS characteristics at 300K and 77K have been experimentally investigated. Carrier transport in a high electric field and hot carrier-induced degradation have been examined in detail. In scaled NMOS devices alone, a triode channel transconductance depends strongly on Si surface orientation, but a pentode transconductance does not depend on it. These behaviors are qualitatively discussed with an effective mass model and carrier transport process. The Si surface orientation dependence of hot carrier-induced degradation is found to be related to the number of interface state. Based upon these results, the optimum surface orientation for submicron CMOS devices is discussed.

Power supply voltage for future CMOS VLSI in half and sub micrometer

The trade off between circuit performance and reliability of CMOS devices is theoretically and experimentally examined in detail down to sub micrometer gate length including various effects such as mobility degradation, reliability physics, parasitic capacitances and parasitic resistances. Based upon these cosideration, a new scaling scenario has been proposed to determine power supply voltage for half and lower sub micrometer CMOS devices. The new scaling scheme has been applied to O.6um CMOS device and it has been verified that the power supply voltage can be scaled down maintaining high circuit performance with high reliability.