Fumitoshi Ito

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international solid-state circuits conference | 2008

Kazushige Kanda; Masaru Koyanagi; Toshio Yamamura; Koji Hosono; Masahiro Yoshihara; Toru Miwa; Yosuke Kato; Alex Mak; Siu Lung Chan; Frank Tsai; Raul Adrian Cernea; Binh Le; Eiichi Makino; Takashi Taira; Hiroyuki Otake; Norifumi Kajimura; Susumu Fujimura; Yoshiaki Takeuchi; Mikihiko Itoh; Masanobu Shirakawa; Dai Nakamura; Yuya Suzuki; Yuki Okukawa; Masatsugu Kojima; Kazuhide Yoneya; Takamichi Arizono; Toshiki Hisada; Shinji Miyamoto; Mitsuhiro Noguchi; Toshitake Yaegashi

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

Archive | 2006