Fumitoshi Sugimoto

Simultaneous Temperature Measurement of Wafers in Chemical Mechanical Polishing of Silicon Dioxide Layer

The wafer temperature in chemical mechanical polishing (CMP) of silicon dioxide layers was measured. When the temperatures of both the polishing slurry and the polishing pad were controlled at 8° C, the measured wafer temperatures were 10-20° C. The temperature distribution affected the thickness of the polished oxide layer. When the wafer temperature was high, the oxide layer removal rate increased because of the increased reaction of the slurry with the oxide layer. It was clear that there was a linear relationship between the measured wafer temperature and the oxide layer removal rate. The effects of grooving several typical polishing pads for oxide layer polishing were investigated. It was found that grooves on the pad increased the uniformity of the removal of the oxide layer from the wafer.

Advanced Metal Oxide Semiconductor and Bipolar Devices on Bonded Silicon‐on‐Insulators

Silicon-on-insulator devices have problems with both performance and cost. We developed three advanced devices on bonded SOI produced using pulse-field-assisted bonding and selective polishing in an attempt to solve these problems. We tightly bonded highly implanted wafers, epitaxial wafers, and wafers covered with smoothed CVD oxide at temperatures below 1000 o C. We uniformly thinned bonded wafers by grinding, polishing, resistivity-sensitive etching, or selective polishing. We formed buried layers and buried electrodes by bonding and polishing techniques. Our high speed epitaxial-base transistor on 1-μm thick SOI has a cutoff frequency of 32 GHz

Influence of Organic Contamination on Silicon Dioxide Integrity

The influence of organic contamination before oxidation on 8-nm-thick silicon dioxide integrity was studied. Contamination results from the intentional adsorption of dioctyl phthalate (DOP) on silicon wafers. Metal-oxide semiconductor (MOS) capacitors were fabricated on the wafers to measure the electrical characteristics of the oxide. A reduction in the dielectric breakdown field strength of the oxide was found to occur after DOP adsorption of more than 1×1013 mol/cm2. The flat-band voltage shift (ΔVfb) and interface trap charge density (Dit) increased with an increase in the amount of DOP below 1×1013 mol/cm2. Positive charges arose from DOP in the oxide during oxidation, which was determined from a negative ΔVfb. Furthermore, with an increase in the DOP level from 1×1013 to 1×1015 mol/cm2, Dit hardly increased whereas ΔVfb gradually increased. This suggests that positive charges at the silicon-oxide interface are fixed. It is thought that an increase in the amount of positive charge in the oxide reduces the dielectric breakdown voltage. From infrared (IR) adsorption measurement, we found that even after DOP decomposition due to oxidation, positive charges within DOP remained, and they degrade oxide integrity.

Time-Dependent Airborne Organic Contamination on Silicon Wafer Surface Stored in a Plastic Box

The time-dependent airborne organic contamination on a silicon wafer surface in a wafer storage box is studied using a model of the multicomponent organic species adsorption-induced contamination (MOSAIC) linked with the experiment. Both the adsorption rate and the desorption rate of the organic species in the wafer storage box were found to be much lower than those in the clean room air; this result is considered to be consistent with the very small concentrations and the very small transport rates of the organic species in the gas phase in the wafer storage box. The organic contamination in the wafer storage box follows the MOSAIC model similar to that in the clean room air.

Bond Strength of Bonded SOI Wafers

We developed a tensile strength measurement technique for bonded silicon-on-insulator (SOI) wafers. After oxidation, wafers are patterned, prior to bonding, to reduce the bonded area. After bonding and grinding, tensile strength is measured by pulling samples perpendicularly to the interface by holders adhesively fixed to the samples. The strength of bonded SOI wafer annealed at 1100°C for 30 minutes exceeded 2000 kgf/cm2, and samples separated not at the bond interface, but at the Si itself. Both SiO2/Si and SiO2/SiO2 bond strengths increased with annealing temperature. The SiO2/Si bond strength was stronger than that of the SiO2/SiO2 bond for annealing temperatures under 1100°C. The strengths became equal after 1200°C annealing. The initial bond strength was maintained in a heat cycle varying from -65°C to 150°C in air for five months.

Pulse-Field-Assisted Wafer Bonding for Silicon on Insulator

We have developed a pulse-field-assisted bonding technique to give void-free, low-temperature wafer bonding for SOI (silicon on insulator). We bonded a pair of oxided wafers by applying pulses of a few hundred volts across the wafers at 800°C in a 0.1 Pa nitrogen ambient. To reduce the volatile materials on the surfaces of wafers, which cause voids at low temperature, we heated the wafers at reduced pressure. The impulsive electrostatic force deforms the insulating oxide and allows bonding despite surface roughness and wafer warpage. Our pulse-field-assisted bonding reduces both the bonding temperature and time. We obtained a bond strength of over 1700 kgf/cm2 after thermal treatment at 800°C for 1 min. This paper also discusses surface roughness, voids, and bond strength.

A pH-Controlled Chemical Mechanical Polishing Method for Thin Bonded Silicon-on-Insulator Wafers

A pH-controlled chemical mechanical polishing (CMP) method for fabricating largearea ultrathin silicon-on-insulator (SOI) layers with uniform thickness was developed. Using a polishing reagent with the pH and colloidal silica concentration lowered, together with grooves fabricated on the SOI layer to expose the insulating oxide, the polishing rate clearly decreased leaving a uniform 0.1-µ m-thick SOI layer. An SOI layer with superior thickness uniformity (±0.01 µ m) across 5-by-5-mm SOI-Si islands was obtained. The thickness uniformity across the wafers was decreased to ±0.07 µ m. In this technique, the end point for polishing was controlled to form thin SOI layers with uniform thickness.

Optimization of contact hole lithography for 65-nm node Logic LSI

Patterning of contact/via is a difficult issue for the optical lithography for each successive generation of LSIs. We examined a number of approaches to obtain a large process window and found that a dry ArF exposure tool with a large depth of focus (DOF) can form 100 nm contact holes. Our experimental results show that enough DOF can be obtained for various layouts by using sub-resolution assist feature (SRAF) technology and a unique illumination technology.