Y. Le Friec

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

In this paper, the first SON (Silicon On Nothing) devices with metal gate are presented. Extremely thin fully depleted Si-films are recognized to be integrable with single-metal gate (mid-gap) due to their intrinsically low threshold voltage. In this work we present mid-gap CoSi/sub 2/ metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Due to its architecture and to the continuity between SD areas and the bulk, SON transistors allow deep silicidation processing down to the gate oxide, meaning that no more polysilicon is left. SON PMOS devices were performed with 55 nm CoSi/sub 2/ gate length with 5 nm of Si-channel thickness, and show excellent performances (350 /spl mu/A//spl mu/m I/sub on/ with only 0.1 nA I/sub off/ at -1.4 V with T/sub ox/=20 /spl Aring/). The polydepletion is of course suppressed and the gate resistance (<2 /spl Omega///spl square/) is very competitive for RF applications.

Influence of electron-beam and ultraviolet treatments on low-k porous dielectrics

The down scaling of complementary metal oxide semiconductor transistors requires materials such as porous low-k dielectrics for advanced interconnects to reduce resistance-capacitance delay. After the deposition of the matrix and a sacrificial organic phase (porogen), postcuring treatments may be used to create porosity by evaporation of the porogen. In this paper, Auger electron spectroscopy is performed to simultaneously modify the material (e-beam cure) and measure the corresponding changes in structure and chemical composition. X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy measurements in attenuated total reflection mode confirm the Auger results. The porogen removal and matrix cross-linking result in the formation of a Si–O–Si network under e-beam or ultra violet cure. The possible degradation of these materials, even after cure, is mainly due the presence of Si–C bonds.

65 nm device manufacture using shaped E-Beam lithography

In this paper, SRAM cell device manufacture using shaped electron beam lithography was developed. TEM view of SRAM cell was showed.

Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.

Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectrics interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.

Reliability failure modes in interconnects for the 45 nm technology node and beyond

This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.