G. Kerrien

3D Mask modeling with Oblique incidence and Mask Corner rounding effects for the 32nm node

The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.

Tracking of design related defects hidden in the random defectivity in a production environment

For mature technologies, main yield detractor is random defectivity. Nevertheless, some devices present higher defectivity than rest of devices. Out of process accident, design related defect is one of suspected root cause. Also, design-based defect type is expected to increase as technology node decreases. Determining origin of these additional systematic defects is not easy as these defects are usually residual for technologies in production, not always predictable by OPC simulator (ex: void defect in active STI structure), and at least hidden by random defectivity after classical wafer inspection control. In this paper, an automatic flow to track systematic defects within global defectivity is presented. This flow starts with a relevant selection of several inspection defect files for a given layer. Then the Design Based Binning (DBB) tool performs a fine alignment of the whole multi inspection defect data set with design file. The resulting aligned defect file is treated by an efficient pattern matching algorithm to generate a design-based binning (DBB) defect file. The integration of this output defect file into a defect database allows easy defect analysis and statistical correlation to electrical results. An example of a suspected design-based defect analysis for a 90nm node device is presented at the end of this paper.

Three-dimensional mask effects and source polarization impact on OPC model accuracy and process window

As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical Proximity Correction (OPC) models grows due to the lithographers need to ensure high fidelity in the mask- to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored. Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These effects can be used to improve model accuracy and to better predict the final process window. In this paper, the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types. Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.

Study of SRAF placement for contact at 45 nm and 32 nm node

At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the depth of focus starts to be very limited. Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field region of a Contact layer mask enforces the edges movement to stop very quickly. The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated after inverse lithography, it is important to know what their behavior is, in term of size and placement. In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us to establish the trends for size and placement of the SRAF. Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at 45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the complexity by adding additional SRAF.

Model-based mask verification

One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model. The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing has become ever more complex throughout the years so properly modeling this portion of the process has the potential to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we will show results of a new approach that incorporates mask process modeling. We will also show results of testing a new dynamic mask bias application used during OPC verification.

Tracking of design related defects hidden by random defectivity in production environment

For mature technology nodes, main yield detractor is random defectivity. Nevertheless, some devices can show higher defectivity than rest of devices. Out of process accident, design related defect is one of suspected root cause. Also, design-based defect category is expected to increase as technology node decreases. Determining origin of these additional systematic defects is not easy as these defects are usually residual for technologies in production, not always predictable by OPC simulator (ex: void defect in active STI structure), and at least hidden by random defectivity after in-line wafer inspection control. In this paper, an automatic flow to track systematic defects within global defectivity is presented. This flow starts with a relevant selection of several inspection defect files for a given device. Then the Design Based Binning (DBB) tool performs a fine alignment of the whole multi wafer inspection data set with design file. The resulting aligned defect file is treated by an efficient pattern matching algorithm to generate a design-based binning (DBB) defect file. The integration of this output defect file into a Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.

Characterization of inverse SRAF for active layer trenches on 45-nm node

Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers. This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process optimization is done for minimum pitch dense lines. Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features (SRAF) to assist the patterning of isolated trenches structures. Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability. Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF for trenches.

32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

Si-photonics waveguides manufacturability using advanced RET solutions

Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit (PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is why printing fidelity is very challenging on photonics patterns. In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool design and does not need any retargeting step before OPC. We will compare these two flows on various Si- Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an industrial environment.

Impact of modelisation pixel size on OPC consistency

In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs, depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures like SRAM for example, where mismatching between gates can cause major issue. There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to identify and solve the root cause of the problem. We will study the relationship between the pixel size and the consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we may optimize pixel size for a full layout.