Vincent Farys

The measurement uncertainty challenge for the future technological nodes production and development

With the continuous shrinkage of dimensions in the semiconductor industry, the measurement uncertainty is becoming one of the major component that have to be controlled in order to guarantee sufficient production yield for the next technological nodes production. Thus, CD-SEM and Scatterometry techniques have to face new challenges in term of accuracy and subsequently new challenges in measurement uncertainty that were not really taken into account at the origin of their introduction in production. In this paper, we will present and discuss results about the accuracy requirements related to key applications for advanced technological nodes production. Thus, we will present results related to OPC model precision improvement by using suitable reference metrology model based on the 3D-AFM technique use. An interesting study related to 193 resist shrinkage during CD-SEM measurement will be also presented and therefore the impact on measurement uncertainty will be discussed. Finally we will conclude this paper by showing the potential industrial benefits to use a simple but relevant 3D-AFM reference metrology model use into the semiconductor production environment.

3D Mask modeling with Oblique incidence and Mask Corner rounding effects for the 32nm node

The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.

Imaging performance and challenges of 10nm and 7nm logic nodes with 0.33 NA EUV

The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.

SRAF enhancement using inverse lithography for 32nm hole patterning and beyond

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important mask writing time due to the shotcount 4. In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited. Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of DOF and Runtime performance for hole patterning

Template affinity role in CH shrink by DSA planarization

Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.

Advanced OPC Mask-3D and Resist-3D modeling

The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.

ARC stack development for hyper-NA imaging

The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle. In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.

Three-dimensional mask effects and source polarization impact on OPC model accuracy and process window

As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical Proximity Correction (OPC) models grows due to the lithographers need to ensure high fidelity in the mask- to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored. Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These effects can be used to improve model accuracy and to better predict the final process window. In this paper, the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types. Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.

A novel mask proximity correction software combining accuracy and reduced writing time for the manufacturing of advanced photomasks

The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data volumes continuously grows. Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity effect correction is able to meet the dual challenge of the new generation of masks. Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the Inscale software package from Aselta Nanographics. We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy and e-beam write time.

Demonstration of an effective flexible mask optimization (FMO) flow

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.