G. N. Nazarova

Development perspectives for radiation-hard shf transmit/receive LSI's for applications of SOI CMOS technology

The present paper concerns the study of SOI MOS transistors RF performance for 0.35-μm domestic digital SOI CMOS technology. A specialized library of RF elements and comprehensive set of SOI RF IP-blocks, including mixers, VCOs, amplifiers, ADC, PLL and frequency divider have been designed and measured. The possibility to design radiation-hard RF transceiver LSIs based on the domestic SOI CMOS technology is confirmed as per the total dose, dose rate and SEE testing results.

Design of passive elements for monolithic silicon-germanium microwave ICs tolerant to ionizing radiation

Techniques for the design of passive elements for monolithic silicon-germanium microwave ICs, tolerant to ionizing radiation have been developed with regard to specific features of the design of microwave passive elements on conducting silicon substrates. A set of the elements for operation at frequencies up to 24 GHz has been designed and fabricated, which includes transmission lines, inductances, and symmetrical transformers for application in a user library for the silicon-germanium BiCMOS technology with design rules of 0.25 μm.

SEE Testing Results for RF and Microwave ICs

A short overview of single event effects for a variety of RF and microwave ICs is presented. New results obtained at the SPELS test center have been used along with published data.

The circuit and functional blocks for radiation-hard transceiver LSICs in SOI CMOS

The results of designing a set of basic circuit and functional blocks (amplifying, oscillating, mixing, etc.) to construct the radiation-hard transceiver CMOS Silicon-on-Insulator (SOI) large-scale integration circuits (LSICs) are presented. It was established experimentally that the test chips of the circuit and functional blocks (CFBs) produced by domestic CMOS SOI technologies at a feature size of 0.35 µm are functionally operable in the frequency range of 1 MHz to 1.8 GHz, and the values of the main parameters are close to the calculated ones. The results of the experimental research on the hardness of the developed CFBs to pulse and dose impact of ionizing radiation are presented and the hardness levels were evaluated.

Total Ionizing Dose Effects in Phase-Locked Loop ICs and Frequency Synthesizers

This paper presents a brief overview of total ionizing dose effects for a variety of PLL ICs and PLL-based frequency synthesizer implemented in commercial bulk CMOS, silicon-on-insulator CMOS, BiCMOS and SiGe BiCMOS technology processes with frequency range up to 8 GHz. Total dose sensitivity data of PLL ICs have been obtained at the SPELS test center, based on comprehensive parametric and functional control.

Simulation of IC-packages for RF and MW applications

A new approach to characterization of IC-packages for RF and microwave applications based on electromagnetic simulation and vector measurements is presented. Following the approach the equivalent-circuit parameters and maximum working frequency have been evaluated for a variety of metal-ceramic and metal-glass packages produced domestically.

Long-Term Transient Radiation Effects in SOI CMOS RF ICs

This paper presents the study of transient radiation effects in SOI CMOS RF ICs and discrete MOS transistors. Experiments show that the sensitivity of SOI RF ICs (gain blocks, mixers, VCO etc.) to transient irradiations (dose rate) is mainly determined by the transient response of RF characteristics i.e. output power, output frequency, power / conversion gain, rather than supply transient photocurrent. SOI VCO demonstrates a minimal threshold dose rate (upset-free level) below than 109 rad(Si)/s, limited by the output frequency variations of ±20% and recovery time up to 100 μs with a maximum dose rate of 5×1012 rad(Si)/s. It is also shown that the long-term transient recovery of the RF characteristics and super-linear dependence of the supply photocurrent vs dose rate are the dominating transient radiation effects in SOI CMOS RF ICs.

Small-signal optimization approach to design of microwave signal switch ICs on MOS transistors

This paper presents a technique for optimizing small-signal parameters of monolithic microwave signal switches on MOS transistors. The technique is based on analytical expressions and visual plots that allow us to determine the topological sizes of transistors providing the optimal values of insertion losses and isolation (decoupling). The effect of the parasitic inductance of connecting bondwires on the characteristics of signal switches is investigated; it is shown that parasitic inductance has a minor effect on insertion losses and reflection losses, but causes severe degradation of isolation. Based on the proposed technique, an IP block for a monolithic microwave switch, which can be used as an antenna switch or a composite functional block in multibit step phase shifters and S- or C-band attenuators, is designed. The comparative results of the numerical simulation and experimental investigation of the 0.25 µm CMOS IP block are presented; at the frequency of 1 GHz, the block has an upper linearity bound of at least +17 dBm, insertion losses of not more than 0.6 dB, and isolation not worse than -37 dB.