Seung-Dong Yang

Investigation of zinc interstitial ions as the origin of anomalous stress-induced hump in amorphous indium gallium zinc oxide thin film transistors

In this paper, we investigated an anomalous hump in the bottom gate staggered amorphous indium-gallium zinc oxide thin-film transistors. During the positive gate bias stress, a positive threshold voltage shift is observed in transfer curve and an anomalous hump occurs as the stress time increases. The hump becomes more serious as the gate bias stress increases while it is not observed under the negative bias stress. From the simulation of a long range migration of zinc interstitial ions (Zni) and the measurement of the diode characteristics after the constant positive bias stress, the origin of the hump can be explained by the migration of the positively charged mobile Zni during the constant positive gate bias stress, which can be conformed by increasing the concentration of Zni from the result of the Auger ZnL3M4.5M4.5 spectra.

Crystal Quality Effect on Low-Frequency Noise in ZnO TFTs

The effect of ZnO active film quality on the low-frequency noise behavior in ZnO thin-film transistors has been investigated. The film crystalline is varied by differentiating the thickness and adding postannealing. To discriminate the origin of 1/f noise, the gate bias dependence of noise spectra is investigated. It is found that the number fluctuation noise model related with trapping/detrapping by traps near the interface becomes dominant as the crystal quality improves, which is also confirmed by another noise parameter, i.e., α Extracted αapp can also well explain the electrical characteristics.

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = −20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

An analysis on applicability of Ti-doped ZnO films as the channel layer of TFTs

In this paper, Ti-doped ZnO TFTs on SiO2/Si substrates by simultaneous RF sputter of Zn and DC magnetron sputter of Ti are successfully fabricated. With undoped ZnO TFTs, as-grown Ti-doped ZnO are compared with post-annealed Ti-doped ZnO TFTs in the furnace at O2 atmosphere of 300 °C. As the annealing time increases, the electrical characteristics such as sub-threshold slop (SS) and on/off current ratio of Ti-doped ZnO TFT become better. In order to find out the reason of performance improvement, the optical analysis is carried out. The data of XRD and AFM indicate that grain size and RMS (root mean square) roughness increase in accordance with annealing time, and the potential barrier and work function of Ti-doped ZnO is smaller than that of undoped ZnO, which indicates that the performance improvement by post-annealing in O2 atmosphere is due to a crystalline reformation in Ti-doped ZnO films.

Enhanced Photo Current in n-ZnO/p-Si Diode Via Embedded Ag Nanoparticles for the Solar Cell Application

In this study, an n-ZnO/p-Si heterojunction diode with embedded Ag nanoparticles was fabricated to investigate the possible improvement of light trapping via the surface plasmon resonance effect for solar cell applications. The Ag nanoparticles were fabricated by the physical sputtering method. The acquired current-voltage curves and optical absorption spectra demonstrated that the application of Ag nanoparticles in the n-ZnO/p-Si interface increased the photo current, particularly in specific wavelength regions. The results indicate that the enhancement of the photo current was caused by the surface plasmon resonance effect generated by the Ag nanoparticles. In addition, minority carrier lifetime measurements showed that the recombination losses caused by the Ag nanoparticles were negligible. These results suggest that the embedding of Ag nanoparticles is a powerful method to improve the performance of n-ZnO/p-Si heterojunction solar cells.

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage (VT) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Improvement of reliability characteristics using the N 2 implantation in SOHOS flash memory

In this paper, device performance and reliability characteristics are investigated and discussed in Fin-type SONOS and SOHOS flash memory device. We also proposed the N2 implantation method for improvement of reliability characteristics in SOHOS flash memory device. It shows that data retention characteristic in N2 implantation SOHOS device is improved due to the nitrogen induced-deep traps, while its P/E speed is degraded by additional nitrogen in high-k trapping layer.

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Copyright ©2015 KIEEME. All rights reserved. This is an open-access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted noncommercial use, distribution, and reproduction in any medium, provided the original work is properly cited. pISSN: 1229-7607 eISSN: 2092-7592 DOI: http://dx.doi.org/10.4313/TEEM.2015.16.4.183 OAK Central: http://central.oak.go.kr TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS Vol. 16, No. 4, pp. 183-186, August 25, 2015

Investigation of the instability of low-temperature poly-silicon thin film transistors under a negative bias temperature stress

In this work, we analyzed and correlated the hysteresis characteristics and instability under negative bias temperature instability (NBTI) stress in p-channel low-temperature poly-silicon (LTPS) thin-film transistors (TFTs). Positive VTH shifts were observed under the NBTI stress. The hysteresis does not appear to be affected by the NBTI stress; however, when the VG stress voltage is −40 V at 100°C, the hysteresis increases as the stress time increases and VTH shifts with sub-threshold slope (SS) degradation. The hysteresis may increase under the extreme stress condition due to the generation of trap-states.