Ho-Jin Yun

Investigation of zinc interstitial ions as the origin of anomalous stress-induced hump in amorphous indium gallium zinc oxide thin film transistors

In this paper, we investigated an anomalous hump in the bottom gate staggered amorphous indium-gallium zinc oxide thin-film transistors. During the positive gate bias stress, a positive threshold voltage shift is observed in transfer curve and an anomalous hump occurs as the stress time increases. The hump becomes more serious as the gate bias stress increases while it is not observed under the negative bias stress. From the simulation of a long range migration of zinc interstitial ions (Zni) and the measurement of the diode characteristics after the constant positive bias stress, the origin of the hump can be explained by the migration of the positively charged mobile Zni during the constant positive gate bias stress, which can be conformed by increasing the concentration of Zni from the result of the Auger ZnL3M4.5M4.5 spectra.

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

An analysis on applicability of Ti-doped ZnO films as the channel layer of TFTs

In this paper, Ti-doped ZnO TFTs on SiO2/Si substrates by simultaneous RF sputter of Zn and DC magnetron sputter of Ti are successfully fabricated. With undoped ZnO TFTs, as-grown Ti-doped ZnO are compared with post-annealed Ti-doped ZnO TFTs in the furnace at O2 atmosphere of 300 °C. As the annealing time increases, the electrical characteristics such as sub-threshold slop (SS) and on/off current ratio of Ti-doped ZnO TFT become better. In order to find out the reason of performance improvement, the optical analysis is carried out. The data of XRD and AFM indicate that grain size and RMS (root mean square) roughness increase in accordance with annealing time, and the potential barrier and work function of Ti-doped ZnO is smaller than that of undoped ZnO, which indicates that the performance improvement by post-annealing in O2 atmosphere is due to a crystalline reformation in Ti-doped ZnO films.

Enhanced Photo Current in n-ZnO/p-Si Diode Via Embedded Ag Nanoparticles for the Solar Cell Application

In this study, an n-ZnO/p-Si heterojunction diode with embedded Ag nanoparticles was fabricated to investigate the possible improvement of light trapping via the surface plasmon resonance effect for solar cell applications. The Ag nanoparticles were fabricated by the physical sputtering method. The acquired current-voltage curves and optical absorption spectra demonstrated that the application of Ag nanoparticles in the n-ZnO/p-Si interface increased the photo current, particularly in specific wavelength regions. The results indicate that the enhancement of the photo current was caused by the surface plasmon resonance effect generated by the Ag nanoparticles. In addition, minority carrier lifetime measurements showed that the recombination losses caused by the Ag nanoparticles were negligible. These results suggest that the embedding of Ag nanoparticles is a powerful method to improve the performance of n-ZnO/p-Si heterojunction solar cells.

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage (VT) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Improvement of reliability characteristics using the N 2 implantation in SOHOS flash memory

In this paper, device performance and reliability characteristics are investigated and discussed in Fin-type SONOS and SOHOS flash memory device. We also proposed the N2 implantation method for improvement of reliability characteristics in SOHOS flash memory device. It shows that data retention characteristic in N2 implantation SOHOS device is improved due to the nitrogen induced-deep traps, while its P/E speed is degraded by additional nitrogen in high-k trapping layer.

Electrical, Structural and Optical Characteristic Analysis of Al-doped ZnO Film Deposited by Atomic Layer Deposition

Al-doped ZnO film on glass substrate is deposited by ALD in low temperature, using 4-step process (DEZ--TMA-). To find out the optimal film condition for TCO material, we fabricate Al-doped ZnO films by increasing Al doping concentration at , so that the Al-doped film of 5 at% shows the lowest resistivity () and the largest grain size (38.047 nm). Afterwards, the electrical and physical characteristics in Al-doped films of 5 at% are also compared in accordance with increasing deposition temperature. All the films show the optical transmittance over 80% and the film deposited at demonstrates the superior resistivity ().

Improvement of Electrical Performance and Stability in ZnO Channel TFTs with Al Doped ZnO Layer

Recently, ZnO based oxide TFTs used in the flexible and transparent display devices are widely studied. To apply to OLED display switching devices, electrical performance and stability are important issues. In this study, to improve these electrical properties, we fabricated TFTs having Al doped Zinc Oxide (AZO) layer inserted between the gate insulator and ZnO layer. The AZO and ZnO layers are deposited by Atomic layer deposition (ALD) method. I-V transfer characteristics and stability of the suggested devices are investigated under the positive gate bias condition while the channel defects are also analyzed by the photoluminescence spectrum. The TFTs with AZO layer show lower threshold voltage () and superior sub-threshold slop. In the case of shift after positive gate bias stress, the stability is also better than that of ZnO channel TFTs. This improvement is thought to be caused by the reduced defect density in AZO/ZnO stack devices, which can be confirmed by the photoluminescence spectrum analysis results where the defect related deep level emission of AZO is lower than that of ZnO layer.

Analysis of SOHOS Flash Memory with 3-level Charge Pumping Method

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

Channel engineering of ZnO-based thin film transistors using Al2O3 interlayer grown by atomic layer deposition

In this study, an Al2O3 interlayer is grown between the ZnO channel layer and the gate dielectric by atomic layer deposition to improve the electrical characteristics of ZnO-based thin film transistors (TFTs). From the current–voltage measurements, superior electrical performance characteristics are confirmed, such as superior subthreshold swing and on-/off-current ratio. On the basis of the results of X-ray diffraction (XRD) analysis, the enhanced properties can be explained by large grains in the ZnO channel layer that is deposited on Al2O3. However, when ZnO grains are aligned in the (002) direction, the stability characteristics under positive bias stress become inferior, which is considered to be caused by considerable oxygen adsorption at the nonpassivated channel surface owing to Zn polar extension.