Gabriel L. Nazar

Fast single-FPGA fault injection platform

Evaluating the resilience of a given circuit against adverse effects, such as radiation-induced single event upsets, is a complex and frequently time-demanding task. For Field Programmable Gate Arrays (FPGAs), this task has the additional complexity of accounting for faults affecting the configuration memory. For this reason, several works propose techniques to inject and evaluate faults affecting configuration bits. In this work, we propose a novel platform which requires a single FPGA to perform the fault injection, to apply input vectors and to evaluate the correctness of the outputs. It can evaluate complex fault models, such as multiple bit errors that are caused by a single bit flip. Furthermore, it occupies a small portion of the device resources and works at a very high speed, being able to inject and remove a fault in under 10μs.

Implementation comparisons of the QR decomposition for MIMO detection

In the context of decoding multiple-input multiple-output (MIMO) symbols, many approaches rise as promising, such as successive interference cancellation and sphere decoding. The QR decomposition (QRD) of the channel impulse response matrix is a critical point to ensure good performance of the subsequent decoding steps for both approaches. This paper presents a low-complexity hardware architecture for the basic QRD algorithm, which is extended to two improved versions, namely the sorted QR decomposition (SQRD) and the minimum mean-square error SQRD. The main contribution of this work is a comparison of hardware implementations of the three variants and an analysis of their impact on a MIMO-BICM system regarding system communications performance and computational complexity.

Reducing embedded software radiation-induced failures through cache memories

Cache memories are traditionally disabled in space-level and safety-critical applications, since it was believed that the sensitive area they introduce would compromise the system reliability. As technology has evolved, the speed gap between logic and main memory has increased in such a way that disabling caches slows the code much more than in the past. As a result, the processor is exposed for a much longer time in order to compute the same workload. In this paper we demonstrate that, on modern embedded processors, enabling caches may bring benefits to critical systems: the larger exposed area may be compensated by the shorter exposure time, leading to an overall improved reliability. We describe the Mean Workload Between Failures, an intuitive metric to evaluate the impact of enabling caches for a given generic application error rate. The proposed metric is experimentally validated through an extensive radiation test campaign using a 28 nm off-the-shelf ARM-based SoC as a case study. The failure probability of the bare-metal application is decreased when the L1 cache is enabled but increased when L2 is also enabled. We also discuss when L2 caches could make the device more reliable.

Accelerated FPGA repair through shifted scrubbing

As critical systems make more and more use of high performance FPGAs, several reliability aspects of these devices come into play. Whenever SRAM-based FPGAs are used, upsets in the configuration memory become a major dependability threat, and must be removed as soon as possible. This is usually accomplished through a process called scrubbing. The traditional scrubbing technique, however, suffers from high energy costs and a long mean time to repair (MTTR). In this work we propose a novel approach to minimize these drawbacks through a triggered shifted scrubbing procedure. The proposed technique exploits the non-uniform distribution of critical bits in the configuration memory of the device to reduce the repair time. It provides an average MTTR reduction of 30% without any changes in the circuit implemented in the FPGA when compared to previous works.

Scrubbing unit repositioning for fast error repair in FPGAs

Field Programmable Gate Arrays (FPGAs) are very successful platforms that rely on large configuration memories to store the circuit functions required by users. Faults affecting such memories are a major dependability threat for these devices, and the applicability of FPGAs on critical systems depends on efficient means to mitigate their effects. The main means to effectively remove such faults, namely configuration scrubbing, consists in rewriting the desired contents of this memory and suffers from high power consumption and a long mean time to repair (MTTR). In this work we propose Scrubbing Unit Repositioning for Fast Error Repair (SURFER), a novel approach to exploit partial dynamic reconfiguration coupled with fine-grained redundancy to greatly reduce the MTTR for FPGAs subject to upsets in their configuration memories.

Fine-Grained Fast Field-Programmable Gate Array Scrubbing

Field-programmable gate arrays provide several relevant advantages for critical systems, such as flexibility and high performance. However, their use in critical systems requires efficient means to mitigate transient faults in the configuration bits. This paper focuses on an alternative mechanism to reduce the repair time of traditional scrubbing approaches. It relies on fine-grained error detection and partial reconfiguration. The fine-grained information is used to dynamically choose an optimized starting position for the scrubbing procedure, reducing the mean repair time. We explore the design space provided by the technique and propose an approach to make resilient diagnosis of configuration faults. The efficiency, scalability, and robustness of the proposed mechanisms are evaluated.

Improving FPGA repair under real-time constraints

Abstract Field Programmable Gate Arrays (FPGAs) are very useful devices for the development of real-time systems, due to their flexibility, performance and reduced design costs. Special care should be taken, however, when considering the occurrence of faults, which is a pressing concern for space applications and critical systems in general, and also growingly relevant for any application using aggressively scaled manufacturing technologies. In the particular case of FPGAs, errors in the configuration memory pose a major dependability threat, and their repair is typically performed by means of scrubbing. The attainable repair time of traditional scrubbing-based approaches, however, may be too long for real-time systems, causing deadlines to be missed. In this work we propose a partial reconfiguration approach that aims at repairing configuration errors under real-time constraints. It relies on fine-grained error detection and a repair mechanism that is finely tuned to maximize the probability of meeting a given deadline.

Fast error detection through efficient use of hardwired resources in FPGAs

Providing high reliability for FPGAs is a demanding task, as such devices may be subject to faults in the configuration bitstream, altering the specified function. Traditional modular redundancy remains the most used technique, due to its high fault coverage and low performance overhead. When high availability and strict real-time deadlines must be considered, however, a short mean time to repair also becomes crucial. The use of fine-grained modules can accelerate error detection, fault diagnosis and bitstream correction, but with increased area costs. In this work, we propose the use of hardwired resources found in state-of-the-art FPGAs to provide fast and area efficient fine-grained error detection. Experimental results show an average speed up in error detection of 7.68 times with only 3.2% more area overhead, when compared to coarse-grained modular redundancy.

Evaluating the effectiveness of a diversity TMR scheme under neutrons

This paper explores the concept of Design Diversity Redundancy (DDR) applied to SRAM-based FPGAs as a proposal to increase system reliability. Three different implementations of an 8×8 matrix multiplication associated to majority voters were used to build a Diversity Triple Modular Redundancy (DTMR) scheme. The whole architecture was prototyped on a Xilinx Virtex5 FPGA and exposed to a neutron source for approximately 21 hours in order to investigate the occurrence of Single Event Effects. In addition, a fault injection campaign was performed in order to compare simulation and experimental data. Results indicate the ability of the system to tolerate faults.

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs

Possible scenarios for future manufacturing technologies increase the desirable features of fault tolerance techniques, such as coping with multiple faults and reducing error latency. On the other hand, current high-end FPGAs present, besides lookup tables and flip-flops, several dedicated components that perform the most commonly required functions. In this paper, we propose an approach to use such resources to efficiently provide fault detection capabilities. We further extend the technique with placement constraints to enhance the detection of faults affecting the routing resources, which is a critical demand for such devices.