José Rodrigo Azambuja

Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications

This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method uses large grain TMR with special voters capable of signalizing the faulty module, and check point states that allow the sequential synchronization of the recovered module. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of check-point states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.

Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs

This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of checkpoint states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.

HETA: Hybrid Error-Detection Technique Using Assertions

This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchdog module to detect SEE faults in microprocessors. These types of faults have a major influence in the microprocessors control flow, causing incorrect jumps in the programs execution flow. In order to protect the system, a non-intrusive hardware module is implemented in order to monitor the data exchanged between the microprocessor and its memory. Since the hardware itself is not capable of detecting all control flow errors, it is enhanced to support a new software-based technique. Also, previous techniques are used to reach higher detection rates. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

Exploring the Limitations of Software-based Techniques in SEE Fault Coverage

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults.

Evaluating Selective Redundancy in Data-Flow Software-Based Techniques

This paper presents an analysis of the efficiency of using selective redundancy applied to registers in software-based techniques. The proposed selective redundancy chooses a set of allocated registers to be duplicated in software in order to provide detection of upsets that occur in the processor hardware and provokes data-flow errors. The selective redundancy is implemented over miniMIPS microprocessor software. A fault injection campaign is performed by injecting single event effect upsets in the miniMIPS hardware. Results show error detection capability, performance degradation and program memory footprint for many case studies. With that, designers can find the best trade-off in using selective redundancy in software.

A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware

This paper presents a non-intrusive hybrid fault detection approach that combines hardware and software techniques to detect transient faults in microprocessors. Such faults have a major influence in microprocessor-based systems, affecting both data and control flow. In order to protect the system, an application-oriented hardware module is automatically generated and reconfigured on the system during runtime. When combined with fault tolerance techniques based on software, this solution offers full system protection against transient faults. A fault injection campaign is performed using a MIPS microprocessor executing a set of applications. HW/SW implementation in a reprogrammable platform shows smaller memory area and execution time overhead when compared to related works. Fault injection results show the efficiency of this method by detecting 100% of faults.

The limitations of software signature and basic block sizing in soft error fault coverage

This paper presents a detailed analysis of the efficiency of software-only techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions can lead designers in developing more efficient techniques to detect these types of faults.

Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors

There is a large set of software-based techniques that can be used to detect transient faults. This paper presents a detailed analysis of the efficiency of dataflow software-based techniques to detect SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results are used to analyze the overhead of data-flow techniques allowing us to compare these techniques in the respect of time, resources and efficiency in detecting this type of faults. This analysis allows us to implement an efficient fault tolerance method that combines the presented techniques in such way to minimize memory area and performance overhead. The conclusions can lead designers in developing more efficient techniques to detect these types of faults.

Evaluating the effectiveness of a diversity TMR scheme under neutrons

This paper explores the concept of Design Diversity Redundancy (DDR) applied to SRAM-based FPGAs as a proposal to increase system reliability. Three different implementations of an 8×8 matrix multiplication associated to majority voters were used to build a Diversity Triple Modular Redundancy (DTMR) scheme. The whole architecture was prototyped on a Xilinx Virtex5 FPGA and exposed to a neutron source for approximately 21 hours in order to investigate the occurrence of Single Event Effects. In addition, a fault injection campaign was performed in order to compare simulation and experimental data. Results indicate the ability of the system to tolerate faults.

Analyzing the Effects of TID in an Embedded System Running in a Flash-Based FPGA

This work analyzes the behavior of a designed embedded system composed of microprocessor, memories and SpaceWire (SpW) links under Total Ionizing Dose (TID) synthesized into a commercial flash-based FPGA from Actel. Two tests were performed: one the FPGA is configured just once at the beginning of the irradiation and the other the FPGA is reconfigured every 5 krad (Si). Results evaluate power supply current (Icc), temperature, function operation and performance degradation.