Gabriella Trucco

The binary perfect phylogeny with persistent characters

The binary perfect phylogeny model is too restrictive to model biological events such as back mutations. In this paper, we consider a natural generalization of the model that allows a special type of back mutation. We investigate the problem of reconstructing a near perfect phylogeny over a binary set of characters where characters are persistent: characters can be gained and lost at most once. Based on this notion, we define the problem of the Persistent Perfect Phylogeny (referred as P-PP). We restate the P-PP problem as a special case of the Incomplete Directed Perfect Phylogeny, called Incomplete Perfect Phylogeny with Persistent Completion, (refereed as IP-PP), where the instance is an incomplete binary matrix M having some missing entries, denoted by symbol ?, that must be determined (or completed) as 0 or 1 so that M admits a binary perfect phylogeny. We show that the IP-PP problem can be reduced to a problem over an edge colored graph since the completion of each column of the input matrix can be represented by a graph operation. Based on this graph formulation, we develop an exact algorithm for solving the P-PP problem that is exponential in the number of characters and polynomial in the number of species.

Explaining evolution via constrained persistent perfect phylogeny

BackgroundThe perfect phylogeny is an often used model in phylogenetics since it provides an efficient basic procedure for representing the evolution of genomic binary characters in several frameworks, such as for example in haplotype inference. The model, which is conceptually the simplest, is based on the infinite sites assumption, that is no character can mutate more than once in the whole tree. A main open problem regarding the model is finding generalizations that retain the computational tractability of the original model but are more flexible in modeling biological data when the infinite site assumption is violated because of e.g. back mutations. A special case of back mutations that has been considered in the study of the evolution of protein domains (where a domain is acquired and then lost) is persistency, that is the fact that a character is allowed to return back to the ancestral state. In this model characters can be gained and lost at most once. In this paper we consider the computational problem of explaining binary data by the Persistent Perfect Phylogeny model (referred as PPP) and for this purpose we investigate the problem of reconstructing an evolution where some constraints are imposed on the paths of the tree.ResultsWe define a natural generalization of the PPP problem obtained by requiring that for some pairs (character, species), neither the species nor any of its ancestors can have the character. In other words, some characters cannot be persistent for some species. This new problem is called Constrained PPP (CPPP). Based on a graph formulation of the CPPP problem, we are able to provide a polynomial time solution for the CPPP problem for matrices whose conflict graph has no edges. Using this result, we develop a parameterized algorithm for solving the CPPP problem where the parameter is the number of characters.ConclusionsA preliminary experimental analysis shows that the constrained persistent perfect phylogeny model allows to explain efficiently data that do not conform with the classical perfect phylogeny model.

Logic Synthesis by Signal-Driven Decomposition

This chapter investigates some restructuring techniques based on decomposition and factorization, with the objective to move critical signals toward the output while minimizing area. A specific application is synthesis for minimum switching activity (or high performance), with minimum area penalty, where decompositions with respect to specific critical variables are needed (the ones of highest switching activity, for example). In order to reduce the power consumption of the circuit, the number of gates that are affected by the switching activity of critical signals is maintained constant. This chapter describes new types of factorization that extend Shannon cofactoring and are based on projection functions that change the Hamming distance among the original minterms to favor logic minimization of the component blocks. Moreover, the proposed algorithms generate and exploit don’t care conditions in order to further minimize the final circuit. The related implementations, called P-circuits, show experimentally promising results in area with respect to classical Shannon cofactoring.

An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs

This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.

An analysis of current waveforms in CMOS logic cells for RF mixed circuits

This paper presents an approach for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in frequency domain has been derived.

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.

A colored graph approach to perfect phylogeny with persistent characters

A main open question related to character-based tree reconstruction is designing generalizations of the Perfect Phylogeny approach that couple efficient algorithmic solutions to the capability of explaining the input binary data, by allowing back mutations of some characters. Following this goal, the Persistent Phylogeny model and the related tree reconstruction problem (the PPP problem) have been recently introduced: this model allows only one back mutation for each character. The investigation of the combinatorial properties and the complexity of the model is still open: the most important such question is whether the PPP problem is NP-hard. Here we propose a graph-based approach to the PPP problem by showing that instances can be represented by colored graphs, while the solutions are obtained by operations on such graphs. Indeed, we give a graph-based characterization of the solutions to the PPP problem by showing the relationship between certain sequences of graph operations on the instance graphs and traversals of a persistent phylogeny solving these instances. Based on this result and on some combinatorial properties of the instance graphs we are able to give a polynomial time algorithm for a restricted version of the PPP problem.

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose Boolean functions with separate lattices, according to the P-circuits decomposition scheme, and then to implement the decomposed blocks with physically separated regions in a single lattice. Experimental results show that about 35% of the considered benchmarks achieve a smaller area when implemented using the proposed decomposition for switching lattices, with an average gain of at least 24%.

Effects of digital switching noise on analog circuits performance

In this paper, we discuss generation of digital switching noise and its propagation through substrate and interconnection parasitics. Effects of switching noise on analog voltage references and radio-frequency blocks are presented. Both simulated and measured results confirmed that crosstalk effects are strongly dependent on substrate and package type. Isolation strategies must be specifically designed for a mixed-signal chip, as they could even worse crosstalk if they are not properly designed accounting for values of parasitics.

Synthesis on switching lattices of Dimension-reducible Boolean functions

In this paper we study the switching lattice synthesis of a special class of regular Boolean functions called D-reducible functions. D-reducible functions are functions whose points are completely contained in an affine space A strictly smaller than the whole Boolean cube {0, 1}n. The D-reducibility of a function f can be exploited in the lattice synthesis process: the idea is to independently find lattice implementations for the characteristic function of the subspace A and for the projection of f onto A, and to compose them in order to construct the lattice for f. The overall lattice area can be further reduced exploiting the peculiar structure of the affine subspaces of {0, 1}n. To this aim, we propose a method for implementing compact lattice representations of affine subspaces whose characteristic function is represented by the product of single literals and EXOR factors of two literals. The experimental results validate the proposed approach.