Giorgio Boselli

An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs

This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.

An analysis of current waveforms in CMOS logic cells for RF mixed circuits

This paper presents an approach for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in frequency domain has been derived.

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.

Effects of digital switching noise on analog circuits performance

In this paper, we discuss generation of digital switching noise and its propagation through substrate and interconnection parasitics. Effects of switching noise on analog voltage references and radio-frequency blocks are presented. Both simulated and measured results confirmed that crosstalk effects are strongly dependent on substrate and package type. Isolation strategies must be specifically designed for a mixed-signal chip, as they could even worse crosstalk if they are not properly designed accounting for values of parasitics.

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to the current pulses drawn from voltage supplies in mixed analog-digital CMOS ICs. To this end, two test chips were designed in 0.18-μm CMOS technology. The two test chips were integrated and then mounted on a board with and without package to compare measurements on chips mounted in package and mounted on board. To ensure that the differences between measurements are only due to the assembling technique, the same printed circuit boards were used for both chip-in-package and chip-on-board. Moreover, the experimental setup was carefully arranged so as not to introduce further disturbances due to external connections or noise sources. Both ICs were extensively simulated by using a realistic model of on-chip and off-chip parasitics to study what happens in the analog section when digital switching noise is injected. Simulations results, confirmed by test chip measurements, demonstrate that disturbances due to switching currents in digital blocks propagate through substrate, package, and interconnection parasitics and affect analog voltages, thus degrading the circuit performance. Therefore, reduction of parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends.

Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs

In this paper we present an approach to analyze effects of digital switching noise on sensitive nodes of the analog section in mixed analog/digital CMOS integrated circuits. As well known, a pre-layout estimation of digital switching noise is a very important target in mixed-signal system-on-chip design.To speed up simulation time, we analyzed the digital and the analog section separately. Digital switching current are evaluated using a dedicated simulation algorithm, while propagation of digital disturbances and their effects on analog blocks are simulated with SPICE. The flexibility of this approach allows us to evaluate the effects of package parasitics, of different switching noise amplitudes, and of different current pulse durations on the same analog circuit, while keeping computational cost and simulation time at low levels.The proposed case study is represented by a flash ADC, acting as analog noise collector, and a set of disturbances due to the current consumption of a two phase clock generator, acting as digital noise generator.

Simulation of crosstalk through bonding and package in mixed-signal CMOS ICs

This paper presents an approach for the simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in time domain has been derived. This representation has been used to perform an analog simulation using SPECTRE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires.

Analysis of Crosstalk Effects on Mixed-Signal CMOS ICs with Different Mounting Technologies

This paper presents an approach for analysis of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A test chip has been integrated and mounted in different ways, in order to compare measurements on chips mounted in package and mounted on board. The chip has been extensively simulated, using a realistic model of on-chip and off-chip parasitics, to study what happens on the analog section when digital switching noise is injected. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through interconnection parasitics, and affect analog voltages, degrading circuit performance. Therefore, reduction of interconnection parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends. Measurements confirm simulation results

Impact of package parasitics on crosstalk in mixed-signal ICs

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A realistic model of bonding and package parasitics has been derived to study digital switching noise injected through bonding interconnections. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through the substrate and affect analog voltages, thus degrading circuit performance. Test structures have been integrated into a test chip mounted with different technologies, in order to compare the measurements on test chips. Measurements confirm simulation results. Chip-on-board mounting technology has better performance with respect to chip-in-package, due to the reduction of parasitic elements.

Simulation of mixed-signal circuits for crosstalk evaluation

This paper presents an approach for simulation of mixed-signal circuits, analyzing possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A closed-form expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach. Simulation results of a non-overlapped two-phase clock generator are presented