Luca Frontini

A new XOR-based Content Addressable Memory architecture

In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose Boolean functions with separate lattices, according to the P-circuits decomposition scheme, and then to implement the decomposed blocks with physically separated regions in a single lattice. Experimental results show that about 35% of the considered benchmarks achieve a smaller area when implemented using the proposed decomposition for switching lattices, with an average gain of at least 24%.

Synthesis on switching lattices of Dimension-reducible Boolean functions

In this paper we study the switching lattice synthesis of a special class of regular Boolean functions called D-reducible functions. D-reducible functions are functions whose points are completely contained in an affine space A strictly smaller than the whole Boolean cube {0, 1}n. The D-reducibility of a function f can be exploited in the lattice synthesis process: the idea is to independently find lattice implementations for the characteristic function of the subspace A and for the projection of f onto A, and to compose them in order to construct the lattice for f. The overall lattice area can be further reduced exploiting the peculiar structure of the affine subspaces of {0, 1}n. To this aim, we propose a method for implementing compact lattice representations of affine subspaces whose characteristic function is represented by the product of single literals and EXOR factors of two literals. The experimental results validate the proposed approach.

Logic synthesis and testing techniques for switching nano-crossbar arrays

Abstract Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.

Radiation-tolerant standard cell synthesis using double-rail redundant approach

In this paper, we describe a new logic family based on a Double-Rail Redundant Approach, that we call D2RA. Each cell receives both the input bits and their negated values, and is made of two main blocks: the first one produces the output bit, the second one the inverted output bit. When a bit and its negated value have the same logic value, then an error occurred. In such a case, the two output bits are set to the same value. This approach allows to avoid single event effects in presence of radiation. The synthesis of the logic function performed by each cell is based on an algorithm that minimizes the number of transistors in a fully-CMOS design approach. We demonstrate that the proposed approach is correct for any number of input variables, and gives the minimum form with respect to the constraints of the logic model.

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Abstract In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by gluing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called P-circuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%.

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Multi-terminal switching lattices are typically exploited for modeling switching nano-crossbar arrays that lead to the design and construction of emerging nanocomputers. In this paper we propose a switching lattice optimization method for a special class of “regular” Boolean functions, called autosymmetric functions. Autosymmetry is a property that is frequent enough within Boolean functions to be interesting in the synthesis process. Each autosymmetric function can be synthesized through a new function (called restriction), depending on less variables and with a smaller on-set, which can be computed in polynomial time. In this paper we describe how to exploit the autosymmetry property of a Boolean function in oder to obtain a smaller lattice representation in a reduced minimization time. The original Boolean function can be constructed through a composition of the restriction with some EXORs of subsets of the input variables. Similarly, the lattice implementation of the function can be constructed using some external lattices for the EXORs, whose outputs will input the lattice implementing the restriction. Finally, the output of the restriction lattice corresponds to the output of the original function. Experimental results show that the total area of the obtained lattices is often significantly reduced. Moreover, in many cases, the computational time necessary to minimize the restriction is smaller than the time necessary to perform the lattice synthesis of the entire function.

Composition of switching lattices for regular and for decomposed functions

Abstract Multi-terminal switching lattices are typically exploited for modeling switching nano-crossbar arrays that lead to the design and construction of emerging nanocomputers. Typically, the circuit is represented on a single lattice composed by four-terminal switches. In this paper, we propose a two-layer model in order to further minimize the area of regular functions, such as autosymmetric and D-reducible functions, and of decomposed functions. In particular, we propose a switching lattice optimization method for a special class of “regular” Boolean functions, called autosymmetric functions. Autosymmetry is a property that is frequent enough within Boolean functions to be interesting in the synthesis process. Each autosymmetric function can be synthesized through a new function (called restriction), depending on less variables and with a smaller on-set, which can be computed in polynomial time. In this paper we describe how to exploit the autosymmetry property of a Boolean function in order to obtain a smaller lattice representation in a reduced minimization time. The original Boolean function can be constructed through a composition of the restriction with some EXORs of subsets of the input variables. Similarly, the lattice implementation of the function can be constructed using some external lattices for the EXORs, whose outputs will be inputs to the lattice implementing the restriction. Finally, the output of the restriction lattice corresponds to the output of the original function. Experimental results show that the total area of the obtained lattices is often significantly reduced. Moreover, in many cases, the computational time necessary to minimize the restriction is smaller than the time necessary to perform the lattice synthesis of the entire function. Finally, we propose the application of this particular lattice composition technique, based on connected multiple lattices, to the synthesis on switching lattices of D-reducible Boolean functions, and to the more general framework of lattice synthesis based on logic function decomposition.

Population count circuits for Associative Memories: A comparison study

This paper proposes a novel population count circuit for Associative Memories (AM)s. Currently, AM chips requires a large number of silicon area for the population count circuitry. For this reason, is necessary an optimization in terms of area for the future AM devices to have a better memory density. A population count circuit counts how many blocks of the AM are in a matching state. If the count sum is greater than a preconfigured threshold, the output wire is set to ‘1’, otherwise is set to ‘0’. In the existing circuits there are, in addition, several control signals that are used to increase the circuit flexibility, but these controls require a large number of transistors and interconnections. The purpose of the proposed circuit is to reduce the number of transistors and interconnections complexity, with the final aim to reduce the occupied silicon area.

Power Distribution Network optimization for Associative Memories

Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity, both at package level and at chip level. This work aims at avoiding “bounce” effects on supply voltages, and at keeping the supply voltage ripple below one hundred millivolts during the comparison mode. A technique to mitigate the voltage ripple consists in placing decoupling capacitors on the Power Delivery Network (PDN). This technique can be applied both at the chip level and at the package level. We show that this technique allows us to keep the power network impedance below 0.1 Ω within the relevant bandwidth of the circuit.