Garima Thakral

Comparative analysis of double gate FinFET configurations for analog circuit design

FinFETs are being adopted as an alternative to nanoscale classical MOSFET for digital circuits. The double-gate (DG) FinFET gives rise to a rich design space using various configurations of the gates. Existing research study the DG FinFET for digital design. However, the effectiveness of the various DG FinFET configurations for the analog design has not received much attention. In this paper, we compare the DG FinFET parameters including transconductance (gm), output resistance (r0), open-circuit gain (gm × r0), transition frequency (fT) including the most important issue, “nanoscale variability”, which are important for analog design. The following three configurations for a fully depleted SOI DG FinFET are analyzed: shorted-gate, independent-gate, and low-power, for both strong inversion and subthreshold operations. Using the results obtained, we present guidelines for DG FinFET based analog design.

Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm

Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have largely automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills and design cycle time. In this paper, two novel design flows are presented for fast multiobjective optimization of nano-CMOS circuits: actual-value optimization and normalized-value optimization. The design flows consider two characteristics for optimization i.e. power and frequency in a current-starved 50nm voltage-controlled oscillator (VCO). Accurate polynomial-regression based models have been developed for power (including leakage) and frequency of the VCO to speedup the design optimization. In the actual-value optimization flow, the power model is minimized using genetic algorithm, while treating frequency >=100MHz as a constraint. The actual-value optimization flow achieved 21.67% power savings, while maintaining a frequency >=100MHz. In the normalized-value optimization flow, the normalized form of these models are subjected to a weighted optimization using genetic algorithm. The normalized-value optimization flow achieved 16.67% power savings, with frequency >=100MHz. It is observed that while the actual-value optimization approach provides a better exploration of the design space, the normalized-value optimization approach provides a ~5x speedup in the computation time.

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nano-CMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-VTh assignment using a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) algorithm, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read SNM. The process variation analysis of the optimal SRAM carried out considering twelve device parameters shows the robustness of the design.

Design of a Reconfigurable Embedded Data Cache

Performance and power consumption are very important aspects of embedded systems design. Several studies have shown that cache memory consumes as much as 50\% of the total power in such systems. Thus, the architecture of the cache governs both performance and power usage of the embedded system. In this paper a new Reconfigurable Embedded Data (RED) cache is proposed especially targeted towards embedded systems. This paper further explores the issues and considerations involved in designing such a reconfigurable cache. The novelty of the RED cache architecture lies in the fact that it can be configured as direct-mapped, two-way, or four-way set associative using a mode selector function. Thus, one cache design can be used for different applications. The module has been designed, simulated and synthesized in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

Variability-aware design of double gate FinFET-based current mirrors

With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance (

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM

r_0

Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study

), compliance voltage (

Double gate FinFET based mixed-signal design: A VCO case study

V_{CV}

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP

) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) configurations. Based on the results obtained, guidelines are presented for the designer for current mirror design using FinFET.

IEEE International Conference on VLSI Design (VLSID)

In this paper, a novel design flow is presented for power minimization of nano-CMOS SRAM (static random access memory) circuits, while maintaining their performance. A 32nm high-K/metalgate SRAM is used as an example circuit. The baseline SRAM circuit is subjected to power minimization using a dual-VTh assignment based on a novel Design of Experiments-Integer Linear Programming (DOE-ILP) approach. However, this leads to a 15% reduction in the Static Noise Margin (SNM) of the SRAM, which is an indicator of the stability degradation of the SRAM. This reduction in the SNM is then overcome using a conjugate gradient optimization, while maintaining the minimum power consumption. The final SRAM design shows 86% reduction in power (including leakage) consumption and 8% increase in the SNM compared to the baseline design. The variability analysis of the optimized cell is carried out considering the variability effect in 12 parameters to study the robustness of the optimal SRAM circuit. An 8 x 8 array is constructed to show the feasibility of the proposed SRAM.