Oghenekarho Okobiah

Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization

This paper explores an ordinary Kriging based metamodeling technique that allows designers to create a model of a circuit with very good accuracy, while greatly reducing the time required for simulations. Regression and interpolation based methods have been researched extensively and are a commonly used technique for creating metamodels. However, they do not take into account the effect of correlation between design and process parameters, which are critical in the nanoscale regime. Kriging provides an improved metamodeling technique which takes into effect correlation effects during the metamodel generation phase. The ordinary Kriging metamodels are subjected to an Ant Colony Optimization (ACO) algorithm that enables fast optimization of the circuit. This design methodology is evaluated on a sense amplifier circuit as a case study. The results show that the Kriging based metamodels are very accurate and the ACO based algorithm optimizes the sense amplifier precharge time with power consumption as a design constraint in an average time of 3.7 minutes (optimization on the metamodel), compared to 72 hours (optimization on the SPICE netlist).

Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective

This paper presents research leading to robust nano-CMOS sense amplifier design by incorporating process variation early in the design process. The effects of process variation are analyzed on the performance of a conventional voltage sense amplifier which is used in most DRAMs. A parametric study is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The Figures of Merit (FoMs) used to characterize the circuit are precharge time, power dissipation, sense delay and sense margin. Statistical analysis is performed to examine the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. In this context, the well-established process-level techniques dual-threshold voltage and dual-oxide thickness are, for the first time, investigated for efficient sense amplifier design. Experimental results prove that the proposed approach improves precharge time by 63.3%, sense delay by 53.6%, sense margin by 39.3%, and power dissipation by 23.3% for 45 nm CMOS.

Fast statistical process variation analysis using universal Kriging metamodeling: A PLL example

The design of Analog Mixed-Signal Systems-on-Chip (AMS-SoCs) presents difficult challenges given the number of design specifications that must be met. This situation is more aggravating in the presence of process variation effects for nanoscale technologies. Existing statistical techniques heavily rely on Monte-Carlo analysis for design parameters in an effort to mitigate the effects of process variation. Such methods, while accurate are often expensive and require extensive amount of simulations. In this paper we present a geostatistical based metamodeling technique that can accurately take into account process variation and considerably reduces the amount of time for simulation. An illustration of the proposed technique is shown using a 180nm PLL design. The proposed technique achieves an accuracy of 0.7 % and 0.33% for power consumption and locking time, respectively, and improves the run time by about 10 times.

Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits

The increasing complexity of modern electronic devices driven by consumer demand and technological advancements presents significant challenges for designers. The reduced feature size and increased capabilities lead to more complex designs as more sub-systems are packed into a single chip. Traditional synthesis and optimization methods which involve CAD tools for accurate simulation are computationally time expensive and even become infeasible especially in designs using nanoelectronic technology due to increased design factors and the exponentially increasing design space. The current objective is to explore techniques that produce optimal designs while reducing the design effort. Metamodeling techniques have been used in this respect to reduce the cost of manual iterative circuit sizing during synthesis. Existing metamodeling techniques however are unable to capture the effects of process variation which are dominant in deep nanometer regions. This work explores Kriging techniques for fast and accurate design optimization of nanoscale analog circuits.

Variability-aware design of double gate FinFET-based current mirrors

With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance (

Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study

r_0

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design

), compliance voltage (

Kriging bootstrapped neural network training for fast and accurate process variation analysis

V_{CV}

Nano-CMOS thermal sensor design optimization for efficient temperature measurement

) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) configurations. Based on the results obtained, guidelines are presented for the designer for current mirror design using FinFET.

Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits

Due to the increasing complexity of nanoscale CMOS circuits and systems integration, full SPICE simulations for silicon accurate results can have run times in the order of days or weeks. This paper presents a methodology that uses a simple Kriging metamodeling technique capable of modeling the correlation effects between parameters, and a simulated annealing algorithm for ultrafast design optimization. The proposed methodology is applied to a clamped bitline amplifier circuit, which shows promising results for increased accuracy in process-aware metamodeling techniques. The error of the metamodels is very small, which is generated in 10.5 min compared to the 72 h taken for an exhaustive simulation. The design optimization performed on the metamodels improves the precharge time of the circuit by 61.15%.