Gennaro Severino Rodrigues

S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

Software-based techniques offer several advantages to increase the reliability of processor-based systems at very low cost, but they cause performance degradation and an increase of the code size. To meet constraints in performance and memory, we propose SETA, a new control-flow software-only technique that uses assertions to detect errors affecting the program flow. SETA is an independent technique, but it was conceived to work together with previously proposed data-flow techniques that aim at reducing performance and memory overheads. Thus, SETA is combined with such data-flow techniques and submitted to a fault injection campaign. Simulation and neutron induced SEE tests show high fault coverage at performance and memory overheads inferior to the state-of-the-art.

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core

This work presents an analysis of the occurrence of software errors at ARM Cortex-A9 dual-core processor. Fault injection results compare the error rate and their causes. Results show that different parallelization algorithms can have different error rates, and that there is a tendency on parallel applications to have more silent data corruption errors than their sequential counterparts.

Reliability on ARM Processors against Soft Errors by a Purely Software Approach

A set of software-based techniques to detect soft errors in embedded ARM processors at low costs is presented. Fault injection results show high fault coverage at performance and memory overheads inferior to state-of-the-art techniques.

Analyzing the Impact of Fault-Tolerance Methods in ARM Processors Under Soft Errors Running Linux and Parallelization APIs

This paper presents an analysis of the efficiency of traditional fault-tolerance methods on parallel systems running on top of Linux OS. It starts by studying the occurrence of software errors at systems presenting different levels of complexity, from sequential bare metal to parallel Linux applications. Then two traditional fault-tolerance mechanisms (triple modular redundancy and duplication with comparison variant) are applied to the applications and their efficiency analyzed. All cases were tested at the single and dual-core versions of an ARM Cortex-A9 processor that is embedded in many commercial system-on-a-chip. The OVP simulator platform is used to instantiate the processor model and to inject faults into the system. Faults are modeled as bit flips in the processor registers. Results show that traditional fault-tolerance algorithms are not efficient enough to protect a whole parallel system running on top of an operating system, given that the operating system itself is a major source of errors.

Evaluating the behavior of successive approximation algorithms under soft errors

This work presents a comparative analysis of successive approximation algorithms with ordinary algorithms under fault injection. Successive approximation algorithms are implemented as a computation loop that approaches the final result for each loop execution. Because of that, we expect that they will present a natural fault tolerance, given that a fault in a given point of the execution may be masked in the next computation loops. This work will evaluate their behavior under simulated fault injection, and executing bare metal and on top of FreeRTOS and Linux operating systems. Results show that successive approximation algorithms presents less silent data corruption errors than most ordinary algorithms, while maintaining the same occurrence of hang errors.

Analyzing the impact of using pthreads versus OpenMP under fault injection in ARM Cortex-A9 dual-core

This paper presents an analysis of the occurrence of software errors at parallel applications using POSIX Threads (Pthreads) versus their OpenMP counterparts and sequential versions. All cases were tested at the ARM Cortex-A9 dual-core processor that is embedded in many commercial SoC available in the market. The OVP simulator platform is used to instantiate the processor model and a fault injection platform injects faults in the system during simulation. We analyze the effect of bit-flips in the registers in both ARM cores during the execution of sequential and parallel versions of the same applications. We then use the fault injection results to analyze the error rate and their causes. Results show that different parallelization algorithms can have different error rates, and that there is a tendency on parallel applications to have more silent data corruption errors than their sequential counterparts when exposed to faults. The results also show a general tendency for Pthreads applications to be more susceptible to silent data corruption errors than their OpenMP counterparts.

Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs

This work proposes a universal method to approximate computational functions. It employs Taylor series to compute approximations and provide results with high accuracy at low cost. A multitude of software and hardware implementation designs are presented and evaluated on a Zynq-7000 APSoC for their area cost, accuracy and time performance. Results show that embedded software approaches tend to provide excellent accuracy at a better cost/accuracy rate, and that hardware projects can save resources costs by slightly relaxing their accuracy requirements.

Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications

This paper evaluates the efficiency and performance impact of a dual-core lockstep as a method for fault-tolerance running on top of FreeRTOS applications. The method was implemented on a dual-core ARM Cortez-A9 processor embedded into the Zynq-7000 APSoC. Fault injection experiments show that the method can mitigate up to 63% on the FreeRTOS applications. This result is very near to the mitigation achievable on bare-metal. Results also show that the overhead caused by the method is higher on FreeRTOS application than it is on bare-metal.