Lixin Ge

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.

Cost and power/performance optimized 20nm SoC technology for advanced mobile devices

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

High performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process induced variations

Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.

Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower Vccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell ≪0.1µm2 below 32nm node.

Modeling MOSFET Drain Current Non-Gaussian Distribution With Power-Normal Probability Density Function

In this letter, a family of power-normal probability density functions is proposed for the asymmetric non-Gaussian distribution of drain current. The results of the proposed methodology are compared against both statistical silicon data and SPICE model Monte Carlo simulation results. Excellent agreement is observed for the power-normal distribution with order of 2. With this proposed distribution, drain current at non-Gaussian high-sigma tail can be predicted by only median and variance extracted from statistical data of a small set of samples (e.g., 1 k). For the first time, a simple analytic model is presented to capture memory read current non-Gaussian tail distribution near -6σ or even beyond, which is a major challenge in memory design for 28 nm technology node and below.

Analog/Mixed-Signal Design in FinFET Technologies

Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.

10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling

The industrys first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.