Michael Han

Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS

Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read sense amplifiers (SA). In this work, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor provides accurate measurement of SA offset from a large sample size and accounts for all proximity effects that may affect the SA offset. The all-digital design of the monitor makes it adequate for low voltage testing, high speed data collection, and ease of migration to newer technologies. Detailed measurement results are provided for two of the most commonly used sense amplifiers at different supply and temperature conditions. Statistical yield estimation using the measured sense amplifier offset shows good correlation with measured yield for a 512Kb SRAM. The monitor is a critical part of SRAM silicon yield validation, which is becoming of increasing importance with technology scaling, and the significant increase in random variations.

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

Test Structure Design, Extraction, and Impact Study of FEOL Capacitance Parameters in Advanced 45nm Technology

In the advanced Low Power (LP) CMOS technology nodes gate-to-soure/drain overlap capacitance (COV), gate-to-contact capacitance (CCO) and gate sidewall fringe capacitance (Cf) have become increasingly important component(s) of transistor parasitic. Accurate extraction and modeling of these parasitic are essential in accurate estimation of circuit performance. In this paper we describe test structure design and extraction of these parasitic components from silicon, which we later correlate to circuit performance. SPICE simulations were performed to substantiate the measurements as needed.

Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm

As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads to fragile silicon backend structure. This in turn brings in reliability issues like LK cracking due to CPI (Chip Package Interaction). The application of flip-chip packaging introduces significant amount of mechanical stress on BEOL (Back-End-Of-Line) at chip-attach processing step due to CTE mismatch, and makes CPI much more challenging and critical for silicon integration. At advanced technology nodes, increasing performance demand of mobile processors coupled with SoC integration is one major driver of bump pitch reduction [1]. Higher I/O count can be achieved with finer bump pitch since die size very likely stays constant if not shrinking further. Cu pillar and ELK material have been introduced in 28nm to realize the pitch reduction and performance gain. Small UBM structure is required with fine pitch Cu pillar which introduces large amount of stress in BEOL layers. On the other hand, while k-value of ELK is reduced by ~20% compared to LK used in previous technologies, its hardness and mechanical modulus have been reduced by ~30%, resulting in major reduction of ELK material strength. In this paper, we present our key learnings from 28nm CPI development with fine pitch Cu pillar. Empirical data based on CPI TV as well as mechanical stress simulations are discussed. UBM dimension which is a critical factor with Cu pillar from CPI perspective is searched at fine pitch, and our data shows CPI robustness limits pitch reduction with Cu pillar if using standard mass reflow process. ELK robustness is also tested at different process corners, including UBM size, bump height and Cu etching module. Some ELK marginality issues are discovered at certain process corner combinations. CPI margin at 28nm with fine pitch Cu pillar is then assessed by correlating mechanical stress simulation to thermal shock testing data. It is shown that min ~15% ELK margin in terms of max ELK stress is necessary to ensure no ELK delamination happening at process corners. Impact of IMC (Intermetallic Compound) and Ni barrier are also studied. It is found that growth of IMC is critical for ELK integrity with mass reflow process. Once IMC is fully grown between Cu pillar and substrate bonding pad, since its stiffness is 2~3X higher than Lead-free solder, mechanical stress on ELK layers increases dramatically. Additional work is carried out to minimize the growth of IMC. It is confirmed that addition of Ni barrier effectively suppresses IMC growth, and increases CPI margin at process corners by considerable amount. Detailed data is presented and final recommendations on fine pitch Cu pillar conclude the paper.

A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications

In this work we have demonstrated, for the first time, a 0.605µm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5GHz speed with ∼500mW at 0.9V and a low Vccmin of 0.6V.

High performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process induced variations

Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.

Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond

This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate bump cell structures are proposed.

Modeling MOSFET Drain Current Non-Gaussian Distribution With Power-Normal Probability Density Function

In this letter, a family of power-normal probability density functions is proposed for the asymmetric non-Gaussian distribution of drain current. The results of the proposed methodology are compared against both statistical silicon data and SPICE model Monte Carlo simulation results. Excellent agreement is observed for the power-normal distribution with order of 2. With this proposed distribution, drain current at non-Gaussian high-sigma tail can be predicted by only median and variance extracted from statistical data of a small set of samples (e.g., 1 k). For the first time, a simple analytic model is presented to capture memory read current non-Gaussian tail distribution near -6σ or even beyond, which is a major challenge in memory design for 28 nm technology node and below.

Low power embedded memory design – process to system level considerations

Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition, circuit techniques at the macro design level, and chip-level integration considerations for low power are described.