George Fikos

Low-voltage low-power accurate CMOS V/sub T/ extractor

Circuits extracting a MOSFETs threshold voltage belong to the general category of bias circuits. Since these circuits do not process signal inputs, their power consumption should be low, while preserving high accuracy and robustness of the output against supply voltage variations and transistor mismatch. In this work, a low-voltage low-power self-biased analog CMOS V/sub T/ extractor is proposed. By utilizing novel feedback on a simple low-voltage V/sub T/ extracting block, the extractor presents less than 0.3% error for wide supply voltage range, and achieves low-power consumption and self-compensation for second-order effects and mismatch. These features are supported by simulation results.

A floating gate CMOS Euclidean distance calculator and its application to hand-written digit recognition

In this work, a Euclidean distance calculator is presented. The circuit comprises of simple computing blocks, their basic element being the floating gate MOSFET (FGMOS), exploiting the merits of this device in designing circuits with low-voltage and rail-to-rail operation. Therefore the overall circuit has the characteristics of modularity, low-voltage and rail-to-rail operation under a single supply voltage, accuracy and simplicity. The circuit is designed with 2/spl mu/ MIETEC CMOS technology and is used in the simulation of a hand-written digit recognition system using the nearest neighbour classification method. The simulation results presented, demonstrate the functionality of the circuit.

A low-voltage, analog power-law function generator

A simple low voltage circuit topology able to generate any positive real number power-law function is presented. The proposed circuit exploits BJTs and is based on piecewise linear approximation of the nonlinear function to be generated. An in-depth mathematical analysis is deployed. The instances of a squarer, a cube-law, a square rooting and cube rooting circuit are thoroughly examined through simulation. The obtained results verify the theoretical calculations

A 32/spl times/32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

A logarithmic response photoarray, incorporating two minimum-sized floating-gate MOSFETs (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for fixed pattern noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32/spl times/32 prototype array implemented in AMS 0.6/spl mu/m CMOS technology, are presented and discussed.

A 32x32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction

A logarithmic response photoarray, incorporating two minimum-sized floating-gate MOSFETs (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for fixed pattern noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32/spl times/32 prototype array implemented in AMS 0.6/spl mu/m CMOS technology, are presented and discussed.

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

A logarithmic response photoarray, incorporating two minimum-sized floating-gate MOSFETs (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for fixed pattern noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32/spl times/32 prototype array implemented in AMS 0.6/spl mu/m CMOS technology, are presented and discussed.

A photocell-array with on-chip normalisation and mismatch compensation

In this paper, a photosensitive array consisting of a novel cell is proposed. The main features of the array are: i) logarithmic conversion of photocurrent to voltage, ii) normalization of each pixels photocurrent towards the average photocurrent, iii) correction of pixels mismatches compensating for fabrication mismatch and iv) flexible interfacing with other circuitry. A 16/spl times/16 prototype array of the proposed cells, along with the corresponding 8-bit decoder have been designed and fabricated through the AMS 0.6/spl mu/ standard CMOS process, and the validity of the above features has been verified through experimental results. The array can be used as a core unit of an image recognition system.