Stilianos Siskos

A current-mode interface circuit for a piezoresistive pressure sensor

An interfacing circuit for piezoresistive pressure sensors based on CMOS current conveyors is presented. The main advantages of the proposed interfacing circuit include the use of a single piezoresistor, the capability of offset compensation, and a versatile current-mode configuration, with current output and current or voltage input. Experimental tests confirm linear relation of output voltage versus piezoresistance variation.

A complete scheme of built-in self-tests (BIST) structure for fault diagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience. >

Low-voltage low-power accurate CMOS V/sub T/ extractor

Circuits extracting a MOSFETs threshold voltage belong to the general category of bias circuits. Since these circuits do not process signal inputs, their power consumption should be low, while preserving high accuracy and robustness of the output against supply voltage variations and transistor mismatch. In this work, a low-voltage low-power self-biased analog CMOS V/sub T/ extractor is proposed. By utilizing novel feedback on a simple low-voltage V/sub T/ extracting block, the extractor presents less than 0.3% error for wide supply voltage range, and achieves low-power consumption and self-compensation for second-order effects and mismatch. These features are supported by simulation results.

Effect of technology on the input transistor selection criteria of a low noise preamplifier

An analysis of a preamplifier noise behaviour, of a low-energy X-rays strip detector for space applications, is presented. The ratio of equivalent thermal noise (enc/sub th/) to enc/sub 1/f/ is defined as the noise comparison ratio (NCR) and is used as the preamplifier input transistor selection criterion. The effect of low-noise preamplifier CMOS technology on noise minimization is thoroughly examined. The preamplifier was designed in AMS 0.6/spl mu/m process, with NMOS and PMOS input MOSFET, and in DMILL 0.8/spl mu/m, with NMOS input MOSFET. Analysis is supported by simulation results, which confirm that the selection of the preamplifier input transistor, for a given shaper, is depended on the noise parameters of the used technology.

A Fast and Compact Analog Buffer Design for Active Matrix Liquid Crystal Displays Using Polysilicon Thin-Film Transistors

This paper presents a new source-follower type analog buffer for active-matrix liquid crystal displays applications, which exhibits high immunity to the threshold voltage variations of the polysilicon (poly-Si) thin-film transistors (TFTs). The functionality of the buffer was verified through simulations. In order for the simulations to be realistic, parameters extraction from fabricated poly-Si TFTs were used.

A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays

In this paper, a new source-follower-type analog buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed. The buffer, consisting of five n-type polysilicon TFTs, one bias voltage, and an additional control signal, exhibits high immunity to threshold voltage and mobility variations. The functionality of the proposed buffer was verified by HSPICE simulations. In order to obtain realistic simulations, the TFT model parameters used for the simulations were extracted from fabricated TFTs using the Silvaco tools (ATLAS). The proposed buffer has 7-bit output voltage with the dynamic output voltage range of 7.5 V ranging from 2.5 to 10 V and with resolution up to 0.03 V

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 μm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

FPGA Architecture Design and Toolset for Logic Implementation

In this paper, the design of an embedded FPGA architecture (i.e. configurable logic blocks) is presented and a complete tool-supported design flow starting from architecture level (i.e. RT-level) and ending with the derivation of the reconfiguration bitstream for the FPGA programming is introduced. The proposed design flow consists of new and modified and extended academic tools. In particular, new tools were developed in order to complement certain critical steps in the implementation flow, since existing academic tools do not combine for a cohesive and complete flow. The remaining design steps are implemented by modified existing academic tools. The FPGA architecture and the tool development is an interactive task, depending on what architectures can be supported by the tools. Using this design support tool set, we designed and simulated in 0.18 TSMC technology an FPGA architecture. More specifically, the detailed design characteristics of the Configurable Logic Block Architecture as well as the interconnect network are determined. Finally, experimental results in terms of energy consumption and delay are given.

A floating gate CMOS Euclidean distance calculator and its application to hand-written digit recognition

In this work, a Euclidean distance calculator is presented. The circuit comprises of simple computing blocks, their basic element being the floating gate MOSFET (FGMOS), exploiting the merits of this device in designing circuits with low-voltage and rail-to-rail operation. Therefore the overall circuit has the characteristics of modularity, low-voltage and rail-to-rail operation under a single supply voltage, accuracy and simplicity. The circuit is designed with 2/spl mu/ MIETEC CMOS technology and is used in the simulation of a hand-written digit recognition system using the nearest neighbour classification method. The simulation results presented, demonstrate the functionality of the circuit.

Analog implementation of erosion/dilation, median and order statistics filters

Abstract In this work an analog implementation of nonlinear filters based on a current-mode sorting/selection network is presented. Three nonlinear filters, an erosion/dilation, a median and an order statistics filter are implemented. The circuits are designed using a new high-speed and very accurate current maximum and minimum selector. These filters could be easily incorporated to smart sensors as well as to smart cameras. SPICE simulation results demonstrate the feasibility of simple analog filters using current-mode techniques.