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Dive into the research topics where S. Vlassis is active.

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Featured researches published by S. Vlassis.


IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 1998

Analog implementation of fast min/max filtering

S. Siskos; S. Vlassis; Ioannis Pitas

An analog implementation of running min/max filters based on current-mode techniques is presented. Switched-current delay cells and current/voltage two inputs min/max selectors are used either for current or voltage inputs respectively. The voltage two input min/max circuit is designed using current conveyors and a modified structure of this is used to implement the running min/max filter for window size n=8. Simulation results demonstrate the feasibility of the proposed implementation, which can be extended to a higher window size.


IEEE Transactions on Circuits and Systems | 2004

Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors

S. Vlassis; S. Siskos

In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The circuits are designed using two FGMOS basic-cells, each one formed by three floating-gate transistors with common source. The first basic cell is connected in voltage mode, while the second one is connected in current-mode configuration in order to implement voltage and current-mode circuits, respectively. Using the basic FGMOS cells, voltage and current squarers, four-quadrant multipliers and a current square rooter are designed. Mismatches and distortion analysis for the proposed circuits have been elaborated. The most important advantages are, rail-to-rail dynamic input range, low distortion and ability for either differential or single-ended input signals. Simulation results demonstrate the feasibility and the accuracy of the circuits.


IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 2002

On the exact realization of LOG-domain elliptic filters using the signal flow graph approach

Costas Psychalinos; S. Vlassis

Logarithmic (LOG)-domain filters can be designed using the signal flow graph (SFG) synthesis approach and an appropriate set of operators. Following the above procedure, all-pole LOG-domain filters that exactly emulate the operation of the inductor-capacitor LC ladder prototype filter can be implemented. In the case of elliptic LOG-domain filters, the transmission zeros are not precisely realized. This is due to the fact that floating capacitors are used, in order to approximately perform the required differentiations. In this paper an alternative SFG representation of the prototype system is done, in such a way that the corresponding filter configuration can be implemented using only LOG-domain lossless integrators and amplifiers. A third-order LOG-domain elliptic filter was simulated in order to confirm the validity of the proposed technique.


Analog Integrated Circuits and Signal Processing | 2002

A High Performance Square-Root Domain Integrator

Costas Psychalinos; S. Vlassis

In this work a true square-root domain integrator configuration is proposed, which is implemented using new current geometric-mean and multiplier/divider blocks. The main advantage of the proposed configuration, in comparison with previous realizations, is the immunity to the body effect. Additional important features are low-voltage operation capability, linear tuneability and design modularity.


international symposium on circuits and systems | 2000

Current-mode non-linear building blocks based on floating-gate transistors

S. Vlassis; S. Siskos

Simple current-mode non-linear computational circuits based on a basic cell built with floating-gate MOS transistors are proposed. The basic cell is used to construct a current square-root circuit, a current squarer and a four-quadrant current multiplier. The circuits offer large input range, low harmonic distortion and high linearity. Spice simulation results verify the performance of the proposed circuits.


Analog Integrated Circuits and Signal Processing | 2000

A Signal Conditioning Circuit for Piezoresistive Pressure Sensors With Variable Pulse-Rate Output

S. Vlassis; S. Siskos

A signal conditioning circuit with variable pulse-rate output for piezoresistive pressure sensors based on CMOS current-mode building blocks is presented. The proposed circuit uses an instrumentation amplifier (IA) based on operational floating amplifiers (OFA), adapted for resistive sensors. This IA offers output current which is independent of tracking and offset errors. Two piezoresistors with current supply are used against four piezoresistors of the basic Wheatstone bridge. A new temperature compensation technique for the pressure sensitivity is described. Also a very advantageous SPICE model for piezoresistive sensors is introduced. Simulation as well as experimental results are included to demonstrate the performance of the circuit.


Analog Integrated Circuits and Signal Processing | 2004

A Square-Root Domain Differentiator Circuit

S. Vlassis; Costas Psychalinos

Companding circuits are very useful blocks for realizing low-voltage, high-frequency analog systems. They are implemented using the translinear principle and the quadratic/exponential I-V characteristic of MOS/BJT transistor. In this paper, a Square-Root Domain differentiator is proposed. It is constructed from an appropriate input stage that converts the input current into a compressed voltage at a capacitors node, and simultaneously senses the capacitors current. The overall configuration of the differentiator also includes a current geometric-mean circuit and a multiplier, both based on a translinear loop. An attractive characteristic of the proposed circuits is their immunity to body effect. HSPICE simulation results were used for evaluating the behaviour of the differentiator.


Analog Integrated Circuits and Signal Processing | 2003

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

S. Vlassis; S. Siskos

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent “corner” error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 μm CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.


international conference on electronics circuits and systems | 1999

Analogue computational circuits based on floating-gate transistors

S. Vlassis; Th. Yiamalis; S. Siskos

In this work analogue computational circuits based on floating gate MOS transistors are introduced. The circuits can operate for both positive and negative input signals with rail-to-rail dynamic input range and can manipulate single-ended or/and differential input signals. The circuits are very suitable for analogue signal processing and neural networks applications.


international conference on image processing | 2001

A floating gate CMOS Euclidean distance calculator and its application to hand-written digit recognition

S. Vlassis; George Fikos; Stilianos Siskos

In this work, a Euclidean distance calculator is presented. The circuit comprises of simple computing blocks, their basic element being the floating gate MOSFET (FGMOS), exploiting the merits of this device in designing circuits with low-voltage and rail-to-rail operation. Therefore the overall circuit has the characteristics of modularity, low-voltage and rail-to-rail operation under a single supply voltage, accuracy and simplicity. The circuit is designed with 2/spl mu/ MIETEC CMOS technology and is used in the simulation of a hand-written digit recognition system using the nearest neighbour classification method. The simulation results presented, demonstrate the functionality of the circuit.

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S. Siskos

Aristotle University of Thessaloniki

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Stilianos Siskos

Aristotle University of Thessaloniki

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Ioannis Pitas

Aristotle University of Thessaloniki

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George Fikos

Aristotle University of Thessaloniki

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V. Kalenteridis

Aristotle University of Thessaloniki

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Ilias Pappas

Aristotle University of Thessaloniki

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Kostantinos Doris

Aristotle University of Thessaloniki

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