George T. Kanellos

10-Gb/s all-optical half-adder with interferometric SOA gates

In this letter, we report an all-optical module that generates simultaneously four Boolean operations at 10 Gb/s. The circuit employs two cascaded ultrafast nonlinear interferometers and requires only two signals as inputs. The first gate is configured as a 2 /spl times/ 2 exchange-bypass switch and provides OR and AND logical operations. The second gate generates XOR (SUM bit) and AND (CARRY bit) Boolean operations and constitutes a binary half-adder. Successful operation of the system is demonstrated with 10-Gb/s return-to-zero pseudorandom data patterns.

Two dimensional polymer-embedded quasi-distributed FBG pressure sensor for biomedical applications

We report on the development of a flexible 2D optical fiber-based pressure sensing surface suitable for biomedical applications. The sensor comprises of highly-sensitive Fiber Bragg Grating elements embedded in a thin polymer sheet to form a 2x2 cm(2) sensing pad with a minimal thickness of 2.5mm, while it is easily expandable in order to be used as a building block for larger surface sensors. The fabricated pad sensor was combined with a low physical dimension commercially available interrogation unit to enhance the portability features of the complete sensing system. Sensor mechanical properties allow for matching human skin behavior, while its operational performance exhibited a maximum fractional pressure sensitivity of 12 MPa(-1) with a spatial resolution of 1x1cm(2) and demonstrated no hysteresis and real time operation. These attractive operational and mechanical properties meet the requirements of various biomedical applications with respect to human skin pressure measurements, including amputee sockets, shoe sensors, wearable sensors, wheelchair seating-system sensors, hospital-bed monitoring sensors.

Clock and data recovery circuit for 10-Gb/s asynchronous optical packets

We demonstrate an all-optical clock and data recovery circuit for short asynchronous data packets at 10-Gb/s line rate. The technique employs a Fabry-Perot filter and a SOA-based ultrafast nonlinear interferometer (UNI) to generate the local packet clock, followed by a second UNI gate to act as decision element, performing a logical AND operation between the extracted clocks and the incoming data packets. The circuit can handle short packets arriving at time intervals as short as 1.5 ns and arbitrary phase alignment.

All-Optical 3R Burst-Mode Reception at 40 Gb/s Using Four Integrated MZI Switches

We demonstrate an all-optical retime, reshape, reamplify (3R) burst-mode receiver (BMR) operating error-free with a 40-Gb/s variable-length asynchronous optical data packets that exhibit up to 9-dB packet-to-packet power variation. The circuit is completely based upon hybrid integrated Mach-Zehnder interferometric (MZI) switches as it employs four cascaded MZIs, each one performing a different functionality. The 3R burst-mode reception is achieved with the combination of two discrete all-optical subsystems. A reshape, reamplify BMR employing a single MZI is used first to perform power equalization of the incoming bursts and provide error-free data reception. This novel approach is experimentally demonstrated to operate error-free, even for a 9-dB dynamic range of power variation between bursty data packets and for a wide range of average input power. The obtained power-equalized data packets are then fed into a 3R regenerator to improve the signal quality by reducing the phase and amplitude jitter of the incoming data. This packet-mode 3R regenerator employs three MZIs that perform wavelength conversion, clock extraction, and data regeneration for every packet separately and operates at 40 Gb/s, exhibiting rms timing jitter reduction from 4 ps at the input to 1 ps at the output and a power penalty improvement of 2.5 dB

Bringing WDM Into Optical Static RAM Architectures

Optical RAM appears to be the alternative approach towards overcoming the “Memory Wall” of electronics, suggesting use of light in RAM architectures to enable ps-regime memory access times. In this communication we take advantage of the wavelength properties of optical signals to present new architectural perspectives in optical RAM structures by introducing the WDM principles in the storage area. To this end, we report on a 4 × 4 WDM optical RAM bank architecture that exploits a novel SOA-based multi-wavelength Access Gate (WDM-AG) and a dual wavelength SOA-based SET-RESET All-Optical Flip Flop (AOFF) as fundamental building blocks. The WDM-AG enables simultaneous random access to a 4-bit optical word encoded in 8 different wavelengths, allowing for the four AOFFs of each RAM row to effectively share the same Access Gate. The scheme is shown to support a 10 Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15 mW/Gbit/s for the WDM-AG and 120 mW/Gbit/s for the AOFFs. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption, while enabling for re-configurability in optical cache mapping.

Optical RAM and Flip-Flops Using Bit-Input Wavelength Diversity and SOA-XGM Switches

In this paper, we demonstrate a novel RAM cell based only on three traveling waveguide semiconductor optical amplifier-cross gain modulation (SOA-XGM) switches. The RAM cell features wavelength diversity in the incoming bit signals and provides Read/Write operation capability with true random access exclusively in the optical domain. Two of the SOA-XGM switches are coupled together through an 70/30 coupler to form an asynchronous flip-flop, which serves as the memory unit. Random access to the memory unit is granted by a third SOA-ON/OFF switch and all three SOAs together form the proposed RAM cell. Proof-of-principle operation is experimentally demonstrated at 8 Mb/s using commercial fiber-pigtailed components. The distinctive simplicity of the proposed RAM cell architecture suggests reduced footprint. The proposed flip-flop layout holds all the credentials for reaching multi-Gb/s operational speeds, if photonic integration technologies are employed to obtain wavelength-scale waveguides and ultrashort coupling lengths. This is numerically confirmed for 10 Gb/s using a simulation model based on the transfer matrix method and a wideband steady-state material gain coefficient.

Recipe for intensity modulation reduction in SOA-based interferometric switches

This paper presents a theoretical and experimental analysis of saturated semiconductor optical amplifier (SOA)-based interferometric switching arrangements. For the first time, it is shown that such devices can provide enhanced intensity modulation reduction to return-to-zero (RZ) formatted input pulse trains, when the SOA is saturated with a strong continuous-wave (CW) input signal. A novel theoretical platform has been developed in the frequency domain, which reveals that the intensity modulation of the input pulse train can be suppressed by more than 10 dB at the output. This stems from the presence of the strong CW signal that transforms the sinusoidal transfer function of the interferometric switch into an almost flat, strongly nonlinear curve. This behavior has also been verified experimentally for both periodically and randomly degraded, in terms of intensity modulation, signals at 10 Gb/s using the ultrafast nonlinear interferometer as the switching device. Performance analysis both in the time and frequency domains is demonstrated, verifying the concept and its theoretical analysis.

Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

We demonstrate a 16GHz physical layer optical cache memory architecture for direct mapping associativity, organized in four cache lines with every line being capable of storing two bytes of optical data. WDM formatting of both the memory address and the optical data words is exploited, while the proposed design relies on the interconnection of subsystems that comprise experimentally proven optical building blocks. The performance of the optical cache is evaluated via physical layer simulations showing successful functionality both during Read and Write operation. Going a step further and considering a higher capacity optical cache module, we present its impact when performing with true processor workload benchmarks in Chip Multiprocessor configurations, employed as a L1 cache shared among multiple cores. Its performance is compared with the conventional electronic CMP topology, where dedicated L1 electronic caches and a shared L2 cache are used, showing that the use of optical 16GHz cache can lead to performance speed-up up to 40% while reducing the cache total capacity requirements by 84%. With optical interconnects having already resulted to high-bandwidth CPU-memory bus solutions, our optical cache architecture forms a fully compatible system solution for bridging the gap between optically connected CPU-cache schemes and high-speed optical RAM cell solutions.

Optical power limiter using a saturated SOA-based interferometric switch

We demonstrate an optical power limiter using a semiconductor optical amplifier (SOA)-based interferometric gate powered by a strong continuous-wave input signal. We present a detailed theoretical and experimental investigation of the power limiting characteristics of saturated SOA-based switches, showing good agreement between theory and experiment.

A 40 Gb/s 3R Burst Mode Receiver with 4 integrated MZI switches

We demonstrate for the first time a 40 Gb/s all-optical 3R burst-mode receiver error-free operation for 9,3 dB power fluctuation between short bursty packets. It consists of a sequence of four integrated MZI switches.