Stelios Pitris

WDM-Enabled Optical RAM at 5 Gb/s Using a Monolithic InP Flip-Flop Chip

We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance.

An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s

We propose and experimentally demonstrate the first all-optical content addressable memory (CAM) cell that comprises an all-optical monolithically integrated InP flip-flop and an optical XOR gate. The experimental results reveal error-free operation at 10 Gb/s for both content addressing and content writing operations. The potential of these memory architectures to allow for up to 40-Gb/s operation could presumably lead to fast CAM-based routing applications by enabling all-optical address look-up schemes.

Monolithically integrated all-optical SOA-based SR Flip-Flop on InP platform

In this paper, we demonstrate for the first time a monolithically integrated InP All-Optical Flip-Flop (FF) based on optical coupled SOA-MZI switches. The experimental proof of principle demonstrated successful error free operation of SR-FF functionality at 5 Gb/s.

First demonstration of an optical content addressable memory (CAM) cell at 10 Gb/s

We experimentally demonstrate the first all-optical Content Addressable Memory (CAM) cell, employing a monolithically integrated InP Flip-Flop and a SOA-MZI XOR gate. Error-free operation during Write operation and Content Addressing is achieved at 10 Gb/s.

All-Optical Tag Comparison for Hit/Miss Decision in Optical Cache Memories

An all optical multi-wavelength tag comparator unit followed by a semiconductor optical amplifier-read access gate (SOA-RAG) is presented for all-optical cache memory architectures. Proof-of-principle operation of the Tag Comparison (TC) circuit as a dual-bit tag-comparison stage is presented by exploiting cross-phase modulation-based XOR logic gates based on SOA-Mach-Zehnder interferometers (SOA-MZIs), in order to decide upon a cache hit or cache miss operation, while the two SOA-MZI outputs control the ON/OFF cross-gain-modulation of the SOA-RAG unit. Experimental error free operation is demonstrated for a 8 × 10-Gb/s wavelength division multiplexing (WDM) formatted optical word signal and a 4 × 10-Gb/s WDM tag.

A programmable Si-photonic node for SDN-enabled Bloom filter forwarding in disaggregated data centers

Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.

Optical interconnect and memory technologies for next generation computing

We demonstrate recent advances in the area of optical RAM-based cache memory technology and in the area of optical interconnect technologies for allowing the deployment of a disintegrated computational setting where off-chip optical cache modules can be connected to cache-light Chip Multiprocessors and DRAM modules. We report on recent experimental results obtained within the FP7 project RAMPLAS and we discuss the disintegration roadmap relying on optical PCB technologies and Si-integrated AWGR and transceiver chips pursued within the recently started project ICT-STREAMS. Finally, we demonstrate the application of optical memory setups in routing applications by proposing optical CAM memories towards the implementation of complete ultra-fast routing look-up tables directly in the optical domain.

Optical interconnect and memory components for disaggregated computing

High-performance server boards rely on multi-socket architectures for increasing the processing power density on the board level and for flattening the data center networks beyond leaf-spine architectures. Scaling, however, the number of processors per board and retaining at the same time low-latency and high-throughput metrics puts current electronic technologies into challenge. In this article, we report on our recent work carried out in the H2020 projects ICT-STREAMS and dREDBox that promotes the use of Silicon Photonic transceiver and routing modules in a powerful board-level, chip-to-chip interconnect paradigm. The proposed on-board platform leverages WDM parallel transmission with a powerful wavelength routing approach that is capable of interconnecting multiple processors with up to 25.6 Tbps on-board throughput, providing direct and collision-less any-to-any communication between multiple compute and memory sockets at low-energy 50 Gbps OOK line-rates. We demonstrate recent advances on the Si-based WDM transceiver, cyclic AWGR router and polymer-based electro-optical circuit board key-enabling technologies, discussing also potential applications in disaggregated rack-scale architectures. We also demonstrate our recent research on optical RAM technologies and optical cache memory architectures that can take advantage of the on-board interconnect technology for yielding true disintegrated computing resolving both power and memory bandwidth bottlenecks of current computational settings.

Thick-SOI Echelle grating for any-to-any wavelength routing interconnection in multi-socket computing environments

As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption. Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.