Theonitsa Alexoudi

Bringing WDM Into Optical Static RAM Architectures

Optical RAM appears to be the alternative approach towards overcoming the “Memory Wall” of electronics, suggesting use of light in RAM architectures to enable ps-regime memory access times. In this communication we take advantage of the wavelength properties of optical signals to present new architectural perspectives in optical RAM structures by introducing the WDM principles in the storage area. To this end, we report on a 4 × 4 WDM optical RAM bank architecture that exploits a novel SOA-based multi-wavelength Access Gate (WDM-AG) and a dual wavelength SOA-based SET-RESET All-Optical Flip Flop (AOFF) as fundamental building blocks. The WDM-AG enables simultaneous random access to a 4-bit optical word encoded in 8 different wavelengths, allowing for the four AOFFs of each RAM row to effectively share the same Access Gate. The scheme is shown to support a 10 Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15 mW/Gbit/s for the WDM-AG and 120 mW/Gbit/s for the AOFFs. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption, while enabling for re-configurability in optical cache mapping.

Dual SOA-MZI Wavelength Converters Based on III-V Hybrid Integration on a

We report on the simultaneous wavelength conversion operation of a dual-element semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI) array hybridly integrated on a 4-μm silicon-on-insulator (SOI) waveguide platform through thermocompression bonding. The SOAs are part of a six-element SOA array with both facets coupled on SOI through vertical and horizontal alignments. The device achieves almost two orders of magnitude reduction in footprint compared with state-of-the-art hybridly integrated SOA-MZI structures. We present for the first time experimental proof of the successful operation of a dual-element SOA-MZI device based on III-V technology on SoI that serves as a wavelength converter, with one SOA-MZI yielding error-free performance with a 0.8-dB power penalty at 12.5 Gb/s and the second SOA-MZI operating error-free at 10 Gb/s with a 2-dB power penalty.

\mu{\rm m}

We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10 -9 BER value using two different types of WDM SRAM row Access Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG. A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS block size scaling towards supporting higher-capacity optical SRAM banks.

-Scale Si Platform

An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 × 10 Gb/s optical words, showing error-free operation with only 0.4-dB-peak-power penalty and requiring a power value of 25 mW/Gb/s.

Optical Cache Memory Peripheral Circuitry: Row and Column Address Selectors for Optical Static RAM Banks

We report on a photonic crystal (PhC) nanolaser based on the heterogeneous integration of a III-V PhC nanocavity on SOI, configured to operate as a Set-Reset Flip-Flop (SR-FF). The active layer is a nanobeam cavity made of a 650 nm × 285 nm InP-based wire waveguide evanescently coupled to 500 nm × 220 nm SOI wire waveguides, demonstrating a record-low footprint of only 6.2 μm2. Injection locking enables optical bistability allowing for memory operation with only 6.4 fJ/bit switching energies and <50 ps response times. Bit-level SR-FF memory operation was evaluated at 5 Gb/s with PRBS-resembling data patterns, revealing error free operation with a negative power penalty.

Column Address Selection in Optical RAMs With Positive and Negative Logic Row Access

Heterogeneous integration of III-V semiconductors on silicon has gained considerable momentum fueled by the need to implement fully functional photonic devices and circuits in a CMOS compatible platform. In this communication, we report on a III-V photonic crystal (PhC) nanocavity, heterogeneously integrated on a silicon-on-insulator platform, to form a PhC nanocavity laser capable of exhibiting two elementary static random access memory (SRAM) cell functions individually, namely switching and latching operations under a high-speed, bit-level regime. As such, the PhC nanocavity laser is examined as a generic logic functions building block, suitable toward multiGb/s energy-efficient, optical SRAM cells with minimal device footprint. The proposed device occupies a total area of only 6.2 μm2 , rendering in this way the demonstrated memory element the smallest among the integrated optical memories presented so far. Bit-level SRAM cell operation requires two elementary functions: the access gate (AG) switching function and set-reset flip-flop (SR-FF) latching function. At first, AG switching operation is evaluated through successful wavelength conversion at 10 Gb/s, revealing a power penalty of 1 dB at 10-9 BER and a switching energy of only 4.8 fJ/bit. Then, fully functional SR-FF memory operation is successfully demonstrated, exhibiting error-free operation with negative power penalty at 5 Gb/s and switching energies of 6.4 fJ/bit. FF operation at higher speeds of 10 Gb/s with reduced switching energy levels of 3.2 fJ/bit is also experimentally investigated. Both logic operations were demonstrated separately with the same PhC nanocavity laser device exhibiting <;50 ps switching times and evaluated under real-type data traffic patterns, raising expectations for beyond 20 Gb/s capabilities toward implementing energy-efficient, ultracompact and high-speed true optical SRAM setups for Datacom applications.

Ultra-compact III-V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s

We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical T-Flip-Flop that employs one SOA-MZI and a feedback loop. Experimental verification is demonstrated at 8MHz using a fiber-based feedback loop implementation.

III–V-on-Si Photonic Crystal Nanocavity Laser Technology for Optical Static Random Access Memories

We present a multi-wavelength SOA-MZI-based access gate and an AWG-based column decoder that control random access of 4×10Gb/s WDM-formatted words into a 4-bit optical RAM row. Error-free decoding with 0.4dB peak power penalty is presented.

All-optical 3-bit counter using two cascaded stages of SOA-MZI-based T-flip-flops

Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Optical RAM row access and column decoding for WDM-formatted optical words

In this letter, low-loss and highly fabrication-tolerant flip-chip bonded vertical couplers under single-mode condition are demonstrated for the integration of a polymer waveguide chip onto the Si₃N₄/SiO₂ passive platform. The passively aligned vertical couplers have a lateral misalignment between polymer and Si₃N₄ waveguide cores of ±1.25 μm. Low-loss operation has been experimentally demonstrated over a wide spectral window of 1480-1560 nm, with measured coupler losses below 0.8 dB for Si₃N₄ taper angles below 1.2°, in good agreement with the calculated values. Furthermore, thermal shock test results show less than 0.1 dB degradation, indicating a robust coupling performance.