Gerhard Enders

Method for fabricating a semiconductor memory device

Double gated transistor

Memory cell having trench capacitor and vertical, dual-gated transistor

DRAM memory having vertically arranged selection transistors

Semiconductor memory with vertical selection transistor

DRAM memory cell and memory cell array with fast read/write access

Trench cell for a DRAM cell array

Method for processing a substrate to form a structure

Buried strap contact for a storage capacitor and method for fabricating it

Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same