Walter Hartner
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Featured researches published by Walter Hartner.
Integrated Ferroelectrics | 1997
G. Schindler; Walter Hartner; Vikram Joshi; Narayan Solayappan; Gary F. Derbenwick; Carlos Mazure
Abstract Stress behavior, results of AES analysis and electrical properties of SBT in dependence of electrode structure and annealing conditions are discussed. Evidence for degradation of the electrical properties of SBT due to diffusion of Ti is presented.
Integrated Ferroelectrics | 1998
M. Grossmann; O. Lohse; D. Bolten; Rainer Waser; Walter Hartner; G. Schindler; Christine Dehm; Nikolas Nagel; Vikram Joshi; Narayan Solayappan; Gary F. Derbenwick
Abstract Imprint is known as a failure mechanism in ferroelectric capacitors due to a voltage shift in the hysteresis curve. A detailed study to investigate the time, temperature and bias voltage dependence of the voltage shift was performed on MOD SBT thin films. Lifetime extrapolation under operating conditions (125 °C) reveal values for the lifetime of well over ten years.
Integrated Ferroelectrics | 1999
Walter Hartner; G. Schindler; Volker Weinrich; Mattias Ahlstedt; Herbert Schroeder; Rainer Waser; Christine Dehm; Carlos Mazure
Abstract After patterning the Platinum/crystalline SrBi2Ta2O9 bilayer by Argon based Reactive Ion Etching (RIE), a degradation of the remanent polarization and leakage current of the capacitors for smaller feature sizes is observed. To simulate the study of the side wall of the capacitors, etching of blanket SBT is used as a model experiment. It is shown that etching of crystalline SBT is damaging the SBT material, resulting in the formation of small crystallites (SEM), the appearance of an unknown peak (XRD) and reduction of the Bismuth content on the SBT surface (AES). Using non-crystalline SBT, neither a degradation of electrical properties for smaller feature sizes nor a structural damage of blanket SBT is found after etching and recrystallization annealing although after etching of non-crystalline SBT also a loss of Bi is seen as indicated by AES. Therefore the following model is proposed: Patterning the Pt/crystalline SBT capacitor leads to a Bi deficient edge of the dielectric. Due to the crystalli...
Archive | 1997
G. Schindler; Walter Hartner; Carlos Mazure; Narayan Solayappan; Vikram Joshi; Gary F. Derbenwick
Archive | 1999
Walter Hartner; G. Schindler; Carlos Mazure-Espejo
Archive | 1998
Vikram Joshi; Narayan Solayappan; Walter Hartner; G{umlaut over }nther Schindler
Archive | 1998
Walter Hartner; Frank Hintermaier; Guenther Schindler; Volker Weinrich
Archive | 1998
G. Schindler; Walter Hartner; Dana Pitzer
Archive | 1996
Walter Hartner; Alexander Dr Rer Gschwandtner; Carlos Dr Rer Nat Mazure
Integrated Ferroelectrics | 1998
Vikram Joshi; Narayan Solayappan; Walter Hartner; G. Schindler; Christine Dehm; Carlos Mazure; Gary F. Derbenwick