Gertjan Hemink

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

Fast and accurate programming method for multi-level NAND EEPROMs

For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.

A 56-nm CMOS 99-

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the worlds first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size

{\hbox {mm}}^{2}

A compact on-chip Error Correcting Code/Circuit (ECC) for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64 M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 10/sup 6/ write/erase cycles.

8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

A compact on-chip ECC for low cost flash memories

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125/spl deg/C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

Fabricated in 56nm CMOS technology, an 8Gb multi-level NAND Flash memory occupies 98.8mm2, with a memory cell size of 0.0075mum/b. The 10MB/s programming and 93ms block copy are also realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks

Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

The stress induced tunnel oxide leakage current occurring in NAND EEPROM memory cells after a large number of WRITE/ERASE (W/E) cycles has been investigated for different W/E pulses. A model for the stress induced leakage current is proposed in which the presence of both holes and neutral oxide traps are a necessary condition for the stress induced leakage current to occur.

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (Vth) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide Vth is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the Vth of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the Vth distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell realizes a very small cell size of 0.67 /spl mu/m/sup 2/ for a 0.35 /spl mu/m rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROMs of 512 Mbit and beyond.

Trapped hole enhanced stress induced leakage currents in NAND EEPROM tunnel oxides

It has been reported that the tunnel oxide of flash E/sup 2/PROM is spoiled by the write/erase sequence of high-field stress and that leakage current (J/sub leak/)is induced at lower voltage, which deteriorates retention time and limits the tunnel oxide thickness of E/sup 2/PROM/sup ./ In order to scale down the tunnel oxide thickness, this paper proposes two new approaches to decrease the leakage current. One is the decreasing impurity concentration in the floating gate poly-Si. The other is to lower annealing process temperature after the floating gate formation. These reduction of J/sub leak/ is more remarkable as the tunnel oxide thickness is thinner. As a result, the tunnel oxide can be scaled down to 6 nm by decreasing gate poly-Si concentration to about 5/spl times/10/sup 19/cm/sup -3/ and lowering annealing temperature to less than 900/spl deg/C. These process will become the key technology to realize 64 Mb E/sup 2/PROM and beyond.<<ETX>>