Jae-Chul Om

Modeling of

A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.

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We have characterized low-frequency noise (LFN) such as 1/f noise and random telegraph noise (RTN) in a NAND flash memory cell string for the first time and shown its fundamental properties. The NAND flash memory cells showed specific LFN characteristics under various conditions such as bit-line bias, word-line bias of a selected cell, and pass bias of the unselected cells in the NAND string. Also, LFN was investigated with the program/erase (P/E) cycling of a cell or all cells in a string, and maximum threshold voltage fluctuation of several tens of millivolts after ~100 000 cycles at the 70-nm technology node was shown. Finally, we predicted the effects of LFN in sub-70-nm NAND flash memories.

Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

The stoichiometric nitride (SiN1.33) and Si-rich nitride (SiN1.1) are characterized by the conductive atomic force microscopy (c-AFM) and electrostatic force microscopy (EFM). Only in SiN1.1, EFM is capable of resolving the domains of positive charges with ∼10nm radius. However, the phase dependence on the bias elsewhere is similar to that of SiN1.33, supporting electron tunneling. The following c-AFM image also exhibits that the local leakage is found exclusively on SiN1.1. We suggest that the hole injection which breaks the SiSi bond occur in the structure with the voltage, increasing the overall conductance.

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In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.

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In this paper the authors proposed a new method to estimate ¿Vth from floating gate NAND flash memory, using charge pumping method to a cell string. Although any cells in a string are selected, this method could be roughly applied to extract ¿Vth. After P/E cycling, the charge pumping method also estimated ¿Vth with moderate pulse amplitude (in this work, at 4.5 V or 5 V). By using our proposed method, not only it is simply possible to estimate ¿Vth of NAND flash memory, but also measurement time can be reduced so much.

Noise and Random Telegraph Noise Characteristics in Floating-Gate nand Flash Memories

Ramping amplitude multi-frequency charge pumping technique is proposed to analyze the nitride traps in silicon?oxide?nitride?oxide?silicon (SONOS) structure. Based on the method, the trap density and the capture cross section at each location in oxide?nitride?oxide (ONO) gate stack can be extracted separately. The trap parameters extracted from the suggested model show that the traps located at tunnel-oxide/nitride interface whose capture cross section is lowest. The cause of large trap density at tunnel-oxide/nitride interface may be due to Si?Si bonding formation as reported in previous works.

Electrostatic force microscopy study about the hole trap in thin nitride/oxide/semiconductor structure

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

MT reliability of MANOS cell was examined from cell array. Lots of retention tail bits occurred even at RT. The fail cells were classified as the manner of q-loss. Defective cell lost abundant charge at early stage, while the q-loss rate of worse cell was faster and lasted in a certain period. Si-cluster in our nitride was supposed to make the worse cell, and this cell redeemed its retention capability by reducing shallow trap in Si-rich nitride.

Extractive method of threshold voltage distribution in floating gate NAND flash memory by using the charge pumping technique

A new charge pumping method is developed and applied to extract the energy distribution of nitride traps in silicon–oxide–nitride–oxide–silicon (SONOS) flash memory. Based on the Frenkel–Poole emission model and the tunneling probability given by Wentzel–Kramers–Brillouin (WKB) approximation, we proposed an advanced model of charge pumping current for SONOS device having thick tunnel oxide (>3 nm). The detection range of trap energy depth in our experiment conditions is 1.06–1.24 eV. The extracted trap density distribution in energy levels of the nitride layer of prepared sample shows the peak trap density of 1.21 ×1020 eV-1 cm-3 at 1.17 eV while the peak trap density extracted using retention model is 6.24 ×1019 eV-1 cm-3 at 1.32 eV. This difference of the peak trap density and energy level at the peak trap density is originated from different tunneling probability of tunnel oxide during the measurement.

New Charge Pumping Method for Characterization of Charge Trapping Layer in Oxide?Nitride?Oxide Structure

We have characterized the low frequency noise (LFN) in the NAND flash memory string, for the first time, and shown its fundamental properties. As a result, the NAND flash memory shown specific LFN characteristics in conditions such as bit-line bias, word-line bias, read current and program or erase state of each cell in a string. Also the LFN was investigated with program/erase (P/E) cycling of a cell or all cells in a string, and shown several tens mV of maximum threshold voltage fluctuation after ~100 k cycling at 70 nm node. Lastly, we have predicted the effects of the LFN in sub-70 nm NAND flash memory.