Gil Heyun Choi

Comparison of TiN Films Deposited Using Tetrakisdimethylaminotitanium and Tetrakisdiethylaminotitanium by the Atomic Layer Deposition Method

TiN films were deposited by the atomic layer deposition (ALD) method using either tetrakisdimethylaminotitanium (TDMAT) or tetrakisdiethylaminotitanium (TDEAT) as the Ti precursor and NH3 as the reactant gas. The TiN films deposited using TDMAT showed two saturated TiN film growth regions which were observed in the temperature ranges between 175 and 190°C and between 200 and 210°C. The TiN films deposited using TDEAT showed a saturated growth rate in the temperature range between 275 and 300°C. The growth rates of the TiN films deposited using either TDMAT or TDEAT were about 5 and 1 A/cycle, respectively. The TiN films grown by the ALD method showed relatively low carbon content compared to the TiN films deposited by other conventional chemical vapor deposition and metalorganic chemical vapor deposition methods using the same precursors. The resistivity of the TiN films deposited by the ALD method was below 1,000 µΩcm. The TiN films deposited using TDEAT showed a lower resistivity than the films deposited using TDMAT. The calculated densities of the TiN films deposited using either TDMAT or TDEAT were about 3.55 and 4.38 g/cm3, respectively. This paper presents a comparison of the characteristics of the TiN films deposited using the two different precursors, TDMAT and TDEAT.

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper metallization

PAALD (plasma assisted atomic layer deposition)-TaN thin films derived from a precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were developed and compared to the thermal ALD-TaN. The deposition rate of the PAALD-TaN process was around /spl sim/0.9 /spl Aring//cycle at 250 /spl deg/C. The resistivity of TaN film by the PAALD was /spl sim/ 366 /spl mu/ohm-cm, while the resistivity by the thermal ALD was not measurable. The PAALD-TaN and thermal ALD-TaN film appeared to have cubic and amorphous phase, respectively. In Cu metallization, as TaN thickness increased, via resistance with thermal ALD-TaN increased dramatically, but via resistance with PAALD-TaN was almost constant and much lower than that with thermal ALD-TaN. Using PAALD-TaN, the diffusion barrier characteristics was also improved in comparison to thermal ALD-TaN.

A novel Al-reflow process using surface modification by the ECR plasma treatment and its application to the 256 Mbit DRAM

A novel Al-reflow process with the electron cyclotron resonance (ECR) plasma treatment for the modification of underlayers was developed in a vacuum isolated sputtering equipment. The key feature of this technology is the introduction of the in-situ ECR plasma treatment for the modification of the surface characteristics such as surface morphology and stoichiometry of the TiN wetting/barrier layer. High wettability of the Al film was obtained on the ECR-treated TiN surface, producing a conformal Al film on the sidewall of the contact hole before the reflow process. Consequently, complete filling of contact holes with Al was achieved in deep sub-micron contact holes with a high aspect ratio. This study has demonstrated that the Al-reflow process can be extended to the process of the devices of 256 Mbit DRAM generation and beyond.<<ETX>>

Low Damage In Situ Contact Cleaning Method by a Highly Dense and Directional ECR Plasma.

In situ electron cyclotron resonance (ECR) plasma cleaning process is applied for the cleaning of sub-half-micron-sized contacts in dynamic random access memory (DRAM) devices. ECR plasma cleaning shows superior performance over reactive ion etch (RIE), RF plasma, and dilute HF wet cleaning methods. The high density but low incident energy of the ECR plasma process minimizes surface damage. In addition, the high directionality of this process effectively removes surface impurities from sub-half-micron-sized contacts, resulting in low and stable contact resistance. The ECR plasma cleaning process also reshapes the contact profile in favor of contact filling by Al reflow and is extremely effective for contact cleaning, especially when H 2 is incorporated to the ECR plasma cleaning process. Thus it shows great promise as a future contact cleaning technology of choice.

A Highly Reliable Cu Interconnect Technology for Memory Device

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.

Nonvolatile MOSFET memory based on high density WN nanocrystal layer fabricated by novel PNL (pulsed nucleation layer) method

We describe a novel technique of fabricating WN nanocrystal memory device. Pulsed nucleation layer (PNL) method is firstly introduced for the formation of uniformly distributed high density (/spl sim/ 1.6 /spl times/ 1012 /cm/sup 2/) nanocrystals with the size of 3 /spl sim/ 5 nm. The WN nanocrystal memory exhibits very large threshold voltage shifts over 3.5 V and good retention and endurance characteristics. Further improvement of memory performances using stacked tunnel barrier and double layer storage node structures was also presented.

A new ALD-TiN/CoSi/sub 2/ contact plug process for reliable and low defect density bit-line integration in sub-quarter micron giga-bit DRAM

This paper reports a new ALD-TiN/CoSi/sub 2/ contact plug process for giga-bit scale DRAM bit-line contacts. Using this technology, we obtained a low contact resistance of 315/spl Omega//cnt for BL/N+ and 1518/spl Omega//cnt for BL/P+ in 0.16 /spl mu/m contacts, as well as a crack-free integration scheme and low level of defect density.

Advanced Al Damascene Process for Fine Trench Under 70nm Design Rule

Due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVD Al. For the process, CVD Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVD TiN and PVD TiN as a wetting layer, which was followed by PVD Al and reflow, then the Al surface was polished with colloidal silica based slurry. In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.

Highly manufacturable sub-100 nm DRAM integrated with full functionality

Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.