Sang Bom Kang

A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.

Ultra-thin EBL (encapsulated barrier layer) for ferroelectric capacitor

A new EBL (encapsulating barrier layer), Al/sub 2/O/sub 3/, was developed in order to preserve the excellent ferroelectric characteristics of PZT capacitors throughout the integration process of FRAMs. From the fully working double-level metal, one-poly, 1T/1C 64 k PZT FRAM, Al/sub 2/O/sub 3/ films with thickness in the range of 60 /spl Aring/ to 100 /spl Aring/ showed excellent barrier properties against the hydrogen attack, reaction between PZT film and IMD, and out diffusion of the volatile component in the capacitor. Moreover, the excellent insulating properties of ultra-thin Al/sub 2/O/sub 3/ EBL offered the reduction of one photo/etch step during the full integration process, which required for the conventional TiO/sub 2/ one.

Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper metallization

PAALD (plasma assisted atomic layer deposition)-TaN thin films derived from a precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were developed and compared to the thermal ALD-TaN. The deposition rate of the PAALD-TaN process was around /spl sim/0.9 /spl Aring//cycle at 250 /spl deg/C. The resistivity of TaN film by the PAALD was /spl sim/ 366 /spl mu/ohm-cm, while the resistivity by the thermal ALD was not measurable. The PAALD-TaN and thermal ALD-TaN film appeared to have cubic and amorphous phase, respectively. In Cu metallization, as TaN thickness increased, via resistance with thermal ALD-TaN increased dramatically, but via resistance with PAALD-TaN was almost constant and much lower than that with thermal ALD-TaN. Using PAALD-TaN, the diffusion barrier characteristics was also improved in comparison to thermal ALD-TaN.

Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition

Post-deposition annealing was investigated for hafnium silicate films deposited on Si substrates by atomic layer deposition. Annealing in NH3 at 750°C incorporated 13 At.% nitrogen in hafnium silicate, and hysteresis significantly depended on film thickness. In contrast, annealing in N2 at 950°C suppressed hysteresis and its dependence on the film thickness. In addition, effective mobility and positive bias temperature instability were improved by N2 annealing of as-deposited hafnium silicate films. Finally, additional N2 annealing following NH3 annealing was effective to obtain highly dense hafnium silicate films with good mobility and optimized nitrogen incorporation.

Investigation of the Contact Resistance between Ti/TiN and Ru in Metal-1/Plate Contacts of Ruthenium Insulator Silicon Capacitor

The contact resistance between Ti/TiN and a Ru electrode in metal-1/plate contacts of ruthenium insulator silicon (RIS) capacitor is investigated. When physical vapor deposition (PVD) Ti/TiN was used as a barrier metal for the metal contact process, a high contact resistance of more than 5000 Ω/contact was obtained due to the oxidation of Ti by the residual oxygen in Ru electrode. On the other hand, with a plasma enhanced chemical vapor deposition (PECVD) Ti/CVD TiN barrier metal, oxidation of Ti was not observed and subsequently a low contact resistance of 15 Ω/contact was obtained. The absence of Ti oxidation with PECVD Ti/CVD TiN can be explained by the reduction of oxygen in the Ru electrode due to the H2 plasma environment in the PECVD-Ti process.

Low temperature processing of conformal TiN by ACVD (advanced chemical vapor deposition) for multilevel metallization in high density ULSI devices

A novel method for low temperature deposition of conformal TiN is reported. ACVD (advanced chemical vapor deposition) is a TiCl/sub 4/-based TiN deposition process which relies on the surface reactions of the adsorbed precursors. With this technique, conformal TiN films with resistivity as low as 130 /spl mu//spl Omega/-cm can be deposited at a deposition temperature of 500/spl deg/C and below. The results from the integration of ACVD-TiN with Si contacts and vias in high density devices indicate that ACVD-TiN is applicable to all levels of multilevel metallization for the next generation of ULSI devices.

PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

Reliability characteristics of high-k gate dielectrics with poly-Si gates and metal inserted poly-Si stack (MIPS) gates are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is V/sub g/=V/sub d/ instead of V/sub g/ at I/sub sub/spl I.bar/max/, while that of high-k/MIPS structure is V/sub g/ at I/sub sub/spl I.bar/max/.

Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

For the first time, we evaluated the breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of the TaN gate and conduction band edge of the Si substrate is accelerated, resulting in an increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electrons and holes is Fowler-Nordheim tunneling.

Effect of enhanced nitridation in PECVD-Ti process for sub-0.2 /spl mu/m metal bit-line common contact process

The implementation of W bit-line enabled the integration of n+ and p+ common contact process at bit-line level. Despite the advantages of the common contact process such as chip-area reduction and elimination of the burden associated with MC dry etch, the immediate implementation of the common contact is difficult due to large increase of p+ contact resistance with high thermal budget capacitor process. The results of the present investigation indicate that the thickness of TiSi/sub 2/ layer must be minimized in order to prevent the out-diffusion of boron into silicide layer. However, simply reducing the thickness of TiSi/sub 2/ presents another problem since it leads to a discontinuous layer of TiSi/sub 2/. Heavily increasing the dosage of p+ plug implantation, which is another way of preventing the depletion of boron dopants, resulted in degradation of p+ contact resistance. Therefore, the dopant out-diffusion alone cannot explain the degradation of p+ contact resistance. In order to minimized the thickness of TiSi/sub 2/, enhanced nitridation after deposition of PECVD-Ti was tested and resulted in effective reduction of the p+ contact resistance by 25%. The TEM and SIMS analysis showed that the additional growth of TiSi/sub 2/ during high thermal budget post annealing was suppressed by the enhanced nitridation. The mechanism responsible for reducing the p+ contact resistance by the enhanced nitridation is attributed to the prevention of the dopant depletion at the interface between TiSi/sub 2/ and Si due to the suppressed formation of additional TiSi/sub 2/.

Effect of TiCl/sub 4/ pre-treatment in PECVD-Ti process for sub-0.2 /spl mu/m metal bit line contacts

The effect of the initial steps in PECVD-Ti process is investigated for the optimization of TiSi/sub x/ formation. A remarkable difference in TiSi/sub x/ formation is observed between pre-plasma and pre-TiCl/sub 4/ treatment in which the initial steps start with H/sub 2/ gas with plasma and TiCl/sub 4/ gas without plasma. TiCl/sub 4/ pre-treatment in the PECVD-Ti process is compared with H/sub 2/ plasma pre-treatment especially for low aspect ratio contacts. PECVD-Ti films with H/sub 2/ plasma pre-treatment results in accumulation of Cl impurities at the interface between Si and TiSi/sub x/, and subsequently results in thinner TiSi/sub x/ and higher contact resistance. With the optimized TiCl/sub 4/ pretreatment, excellent electrical characteristics are obtained in sub-0.2 /spl mu/m bit line contacts.