Gilles Gouget

Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]

We present measurements of GIDL at various temperatures and terminal biases. Besides band-to-band (BBT) tunneling leakage observed at high drain-to-gate voltage V/sub DG/, we also observed trap-assisted-tunneling (TAT) leakage currents at lower V/sub DG/. Based on ISE TCAD simulations of the electric field, we propose analytical models for BBT and TAT GIDL currents suitable for compact modelling.

Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 /spl Aring/ to 13 /spl Aring/) and areas (from 27000 /spl mu/m/sup 2/ to 2 /spl mu/m/sup 2/), this paper describes the effect of gate current on measured capacitance using a standard 10 kHz-to-1 MHz LCR-meter. We show that, in presence of high gate leakage, the series impedance, and also the channel debiasing, have a dramatic effect on observed C(V) curves. We also propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C(V) and provides a solution for process monitoring (such as oxide thickness) and intrinsic capacitance determination for device modeling.

Evidence of Reduced Self Heating with Partially Depleted SOI MOSFET Scaling

The temperature rise in SOI has been measured on two successive generations. This work shows that self-heating effects become less and less severe with both MOSFET and power supply voltage scaling.

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

A detailed analysis of the body potential impact on the performance enhancement of BC pMOSFET when the body is not contacted, is reported in this paper. Investigations on floating-body device behavior reveal that these new floating body effect leads to pMOSFET drive capability increase with lower subthreshold slope, no Ioff degradation and no kink effect. The body potential is mainly governed by the ECB component between the partial n+ poly-gate and n type silicon substrate through the 1.6 nm thin gate oxide. Static characterizations of various layouts and geometries demonstrate that narrow pMOSFET and H gate design provide the highest Ion gain due to higher body potential. Furthermore, it has been found that the largest n+ poly gate area results in the fastest switch-on Id transients.

New length scaling of current gain factor and characterization method for pocket implanted MOSFET's

A new analytical model is proposed for the gain factor channel length dependence /spl beta/(L) observed in advanced MOSFET device architectures with pocket implants. The idea consists of splitting the channel length domain into two regions of different mobility values. This approach has been implemented in the BSIM3V3.2 model for the description of 0.18 /spl mu/m MOSFETs. Very good modeling in a large channel length range for N- and P-MOSFETs is demonstrated.

The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies

This work focuses on what drives the access resistance. Based on TCAD simulations, we evidence that the access resistance does depend on gate voltage. From this statement, after considering an access resistance compact model, we show that the access resistance voltage dependence generates an artificial short channel mobility collapse. Based on actual silicon data we establish link between μo-L and Rac-Vg. In particular this relation predicts that negative resistance could be extracted for narrow devices in agreement with experiments.

Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI

In this work, robust methodologies for parameter extraction using split C-V measurements in FD-SOI structures are developed. These methods enable an automated and robust extraction procedure which is very important from an industrial perspective. The accuracy and robustness of the improved methods are verified using statistical measurements carried out on 28 nm FD-SOI devices and comparison with physical characterization.

Device level modeling challenges for circuit design methodology in presence of variability

CMOS technology scaling to decananometer range has raised the challenge to mitigate the impact of multi-scale process variations ranging from cm to atom-scale and acting as circuit yield detractors. Moreover, circuit applications in Ultra Low Power (ULP) range lead to MOSFET device operation in near threshold regime where it is well established that variability impact on DC/AC electrical characteristics dramatically increases. Variability mitigation techniques are part of process development. In addition, accurate circuit design methodologies are required to determine circuit performance margins versus specifications, and to develop circuit level variability mitigation/compensation techniques, to enable high yield and manufacturable products in presence of variability. In this context, we update device modeling requirements for circuit design, revisit device electrical characterization and compact modeling methodologies needed to support accurate circuit simulation throughout the design space. We focus on spatial variability components at local scale, including systematic layout effects and statistical variability. This approach is illustrated on UTBB FDSOI devices. Device modeling challenge for accurate circuit simulation in presence of variability is better identified.

Sensitivity analysis of C-V global variability for 28 nm FD-SOI

This work describes a statistical model for the C-V global variability of 28 nm FD-SOI using the sensitivities of the capacitance to each process parameter calculated using Leti-UTSOI compact model. The percentage contribution of each process parameter to the total C-V variation is explored to identify the dominant source of variation at different bias conditions. The proposed model provides an alternate method to directly extract the variance of the process parameters from the measured C-V variability.