P. Scheer

Record RF performance of standard 90 nm CMOS technology

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

In this paper, we present the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs based on an explicit formulation of front and back surface potentials that is valid and extremely accurate in all operation regimes. The model provides physics-based consistent description of DC and AC device characteristics; it has been extensively validated against TCAD and hardware data, and fulfills standard requirements from quality assurance and convergence tests for circuit design.

Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

Coupling on-wafer measurement errors and their impact on calibration and de-embedding up to 110 GHz for CMOS millimeter wave characterizations

An investigation of parasitic coupling that occurs when making on-wafer measurement at millimeter wave range is described. Several passive structures-dedicated to de-embedding of MOSFETs-are experimentally studied and compared to HFSS electromagnetic simulations in order to highlight parasitic coupling and identify causes of measurement errors. Suggestions on coupling between adjacent test structures and/or probe to back-end environment are also discussed.

Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 /spl Aring/ to 13 /spl Aring/) and areas (from 27000 /spl mu/m/sup 2/ to 2 /spl mu/m/sup 2/), this paper describes the effect of gate current on measured capacitance using a standard 10 kHz-to-1 MHz LCR-meter. We show that, in presence of high gate leakage, the series impedance, and also the channel debiasing, have a dramatic effect on observed C(V) curves. We also propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C(V) and provides a solution for process monitoring (such as oxide thickness) and intrinsic capacitance determination for device modeling.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters.

4-Port isolated MOS modeling and extraction for mmW applications

This paper reports on the extraction of the small-signal equivalent circuit of 28nm isolated RF MOS transistors using on-wafer 4-port S-parameter measurements up to 50GHz. It shows that modeling accuracy of RF MOS is significantly enhanced via a 4-resistance cross-type substrate network plus an isolation sub-network. In addition, the impact of substrate network on Mason gain is presented. Finally, the whole methodology is shown to be very promising to extract and model RF MOS in sub-threshold region for low power/high frequency applications.

RF noise investigation in High-k/Metal Gate 28-nm CMOS transistors

In order to pursue Moores law, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate (H-k/MG) for CMOS has been a key point to downscale the “equivalent oxide thickness” (EOT). Within this context, this paper intends to investigate RF noise performance of a recent Low Power (LP) 28-nm H-k/MG CMOS Technology. For this purpose, S-parameters have been measured up to 110GHz to accurately extract an RF Small Signal Equivalent Circuit (SSEC), required to extract a two-temperature noise model. The technology offers a minimum noise figure NFmin of 0.8dB (with an associated gain Ga equal to 14dB) @20GHz, for a DC drain current of 135mA/mm: these performances well compete with those previously reported for other H-k/MG technology.

Analysis and modeling of substrate impedance network in RF CMOS

This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.