M. Minondo

Characterization and Modeling of Gate-Induced-Drain-Leakage

We present measurements of Gate-Induced-Drain-Leakage at various temperatures and terminal biases. Besides Band-to-Band tunneling leakage observed at high Drain-to-Gate voltage v DG , we also observed Trap-Assisted-Tunneling leakage current at lower v DG . Based on ISE TCAD simulations of the electric field, we propose analytical models for Band-to-Band and Trap-Assisted Gate-lnduced-Drain-Leakage currents suitable for compact modeling.

LDMOS modeling for analog and RF circuit design

This paper presents a complete SPICE sub-circuit model for a lateral double diffused N-MOS (NLDMOS) in a 0.25 m BICMOS technology. The proposed model accurately simulates single and multifinger devices up to geometry sizes used in the final application. The model is validated in DC, AC and large signal conditions. It accounts for all basic LDMOS phenomena such as graded channel, quasi-saturation and self-heating effects. Such study demonstrates that this sub-circuit approach can compete with recent physically based published compact models and even surpass them in terms of flexibility and portability in numerous simulators.

Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]

We present measurements of GIDL at various temperatures and terminal biases. Besides band-to-band (BBT) tunneling leakage observed at high drain-to-gate voltage V/sub DG/, we also observed trap-assisted-tunneling (TAT) leakage currents at lower V/sub DG/. Based on ISE TCAD simulations of the electric field, we propose analytical models for BBT and TAT GIDL currents suitable for compact modelling.

Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 /spl Aring/ to 13 /spl Aring/) and areas (from 27000 /spl mu/m/sup 2/ to 2 /spl mu/m/sup 2/), this paper describes the effect of gate current on measured capacitance using a standard 10 kHz-to-1 MHz LCR-meter. We show that, in presence of high gate leakage, the series impedance, and also the channel debiasing, have a dramatic effect on observed C(V) curves. We also propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C(V) and provides a solution for process monitoring (such as oxide thickness) and intrinsic capacitance determination for device modeling.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models.

The impact of the substrate preamorphisation on the electrical performances of P+/N silicon junction diodes

Abstract Shallow p+/n junctions are produced by low energy Boron or Boron Fluorine implantation into n-type silicon preamorphised substrate. Preamorphisation step was obtained by high dose Ge+ ions implantation at various energies ranging between 30 to 150 keV. The electrical characteristics of the diodes (reverse current density and noise spectral density) are shown to be strongly dependent on the preamorphisation Ge+ ions implantation energy. Combining electrical analysis with transmission electron microscopy allowed us to correlate the diode behaviour with the extended defects distribution induced by the regrowth of the amorphous layers. We report that these defects, usually named End-Of-Range, strongly affect the electrical performance when located within or close to the space charge region.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters.

Dielectric relaxation characterization and modeling in large frequency and temperature domain: application to 5fF//spl mu/m/sup 2/ Ta/sub 2/O/sub 5/ MIM capacitor

This paper deals with 5fF//spl mu/m/sup 2/ Ta/sub 2/O/sub 5/ MIM (metal-insulator-metal) dielectric relaxation characterization and modeling. The Dow model based on RC poles is reviewed in particular to introduce temperature behavior. An optimized test chip that can be accurately simulated allows us to properly measure memory effect. This enables to obtained dielectric relaxation model over 5 time decades and the whole temperature and voltage operation range. The good agreement of this model with MIM capacitance versus frequency measurements validates this approach.

Electrical characterization and compact modeling of MOSFET body effect

In this paper we report on the impact of the depth dopant profile on MOSFETs threshold voltage shifts induced by bulk biases. This body effect is characterized with an original procedure using experimental data, but also a series of TCAD simulations, including advanced process simulation of the dopant distribution along the depth of the transistor. Finally the impact of the doping profile non-uniformity on the body effect is accounted for within the framework of a charge sheet model.

The impact of the substrate preamorphisation on the electricaI performances of p/sup +//n silicon junction diodes

Shallow p/sup +//n junctions are produced by low energy boron or boron fluorine implantation into n-type silicon preamorphised substrate. The preamorphisation step was obtained by high dose Ge/sup +/ ion implantation at various energies ranging between 30 to 150 keV. The electrical characteristics of the diodes (reverse current density and noise spectral density) are shown to be strongly dependent on the preamorphisation Ge/sup +/ ion implantation energy. Combining electrical analysis with transmission electron microscopy allowed us to correlate the diode behaviour with the extended defects distribution induced by the regrowth of the amorphous layers. We report that these defects, usually named End-Of-Range, strongly affect the electrical performance when located within or close to the space charge region.