Egas Henes Neto

Using Bulk Built-in Current Sensors to Detect Soft Errors

Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption

Using built-in sensors to cope with long duration transient faults in future technologies

Transients spanning more than one clock cycle will challenge soft error tolerant designs for future technologies. To face this problem, a low overhead technique that uses bulk built-in current sensors and recomputation is proposed here.

Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection

This paper presents a parameterized current sensor able to detect transient ionization in the silicon substrate. Each sensor is controlled by a set of trimming bits that can be used to attune the sensitivity of the sensor compensating process and temperature variations. By choosing different configurations in the trimming bits, it is possible to adjust the performance of the sensor, which can increase the number of transistors monitored by a single sensor reducing the area overhead. Monte Carlo simulations are used to evaluate the sensor behavior. Results from a case-study circuit with embedded Tbulk-BICS confirm the efficiency of the technique.

Modeling the sensitivity of CMOS circuits to radiation induced single event transients

An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible.

Single event transients in combinatorial circuits

The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track. This work presents an accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to SEU. The key idea of this work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit, without the need to run circuit simulations. To accomplish the task, but single event transient generation and its propagation through circuit logic stages is characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse (bit flip) which may propagate to the next logic gate or memory element. The propagation of the transient pulse through each stage of logic until it reaches a memory element is also modeled. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is also proposed. The model considers the electrical masking properties of the logic gates through which the pulse propagates. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-tools, intending to make automated evaluation of MOS circuit sensitivity to SEU possible, as well as automated estimation of soft error rate

Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic

In this paper, we propose a new approach for using built-in current sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity

Generation and Propagation of Single Event Transients in CMOS Circuits

The generation and the propagation of radiation induced single event transients (SET) in CMOS circuits are evaluated. An accurate and computer efficient analytical model for SET generation and propagation is proposed. The model allows the rapid determination of the sensitivity of any MOS circuit node to SET, without the need to run circuit level simulations. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. Electrical masking of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. The proposed approach is suitable for integration into CAD-tools, intending to make automated evaluation of circuit sensitivity to SEU possible

Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors

In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.

A built-in current sensor for high speed soft errors detection robust to process and temperature variations

Soft errors can be efficiently detected using built in current sensors connected to the transistors bulk, monitoring currents caused by ionizations in the substrate. However, electrical parameter variations can compromise the functional operation of the sensor. The electrical parameter variations can arise from variations during the fabrication process of nanometer scale technologies, as well as from exposure to radiation. This work presents a parameterized current sensor (Tbulk-BICS), which is based on trimming bits. The Tbulk-BICS is able to compensate electrical parameter variations by digitally adjusting the transconductance. Electrical simulation results show the high detection efficiency of the Tbulk-BICS, even in presence of process and temperature variations.