Giovanni Capuz

Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs

Assembling multi-layer thinned Si chips to form 3D ICs in a fast, reliable, and cost-effective manner is one of the key processes to enable wider application and commercialization of 3D integration. In this paper the essential aspects of process development for stacking multi-layer 3D ICs are investigated. Combining thermo-compression bonding (TCB) process and the usage of pre-applied wafer-level underfill (WLUF) can significantly reduce the process complexity and time. A novel vertical collective bonding method is proposed and experimentally implemented, showing great potential in process improvement and throughput increase. Based on these techniques, stacking of multiple layers of 50 μm thick chips on bottom dies is successfully demonstrated. Daisy chains consisted of TSVs 5 μm in diameter and 20 μm pitch micro joints, in both bump-to-bump (Sn-to-Cu) and TSV-to-bump (Cu-to-Cu) bonding schemes, are connected with good electrical yield between all the stacked layers.

Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond

We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can also be reduced significantly to below 220C and 100MPa. The standalone thin die warpage initially 15μm is reduced to 5.4μm by applying the optimized TCB process. The electrical characterizations show good daisy chain connections between each stacked chip and the resistances are very close to the theoretical values. The cross section SEM proofs good TSV alignment to Cu bump, and TSV nails deform and land nicely onto the Cu bump. Finally, we propose to move forward to die-to-wafer approach and migrate to 10μm bump pitch for advanced package application.

Wafer applied and no flow underfill screening for 3D stacks

As the demand for 3D packaging increases, selecting reliable and cost effective materials to be used to build these complex packages has gained a lot of importance. As current IC technology nodes are becoming “Moore-than-Moore” challenging, thus industry and research institutes alike are trying to find ways of addressing this challenge. The integration of new types of underfill materials in 3D stacking is one very important part of the package material set that will determine its reliability and cost effectiveness. With the introduction of 3D technology, bump sizes and pitches have been scaled down significantly which in turn has also shrank underfill gaps between dies which complicates the assembly of 3D stacks. The need of new underfill materials and underfilling concepts becomes inevitable. It is quite difficult to make traditional capillary type underfills and underfilling methods to work due to the very narrow gaps and fine bump pitches that 3D stacks have. Pre-applied underfills (Wafer Applied or No Flow) with or without fillers (submicron or Nano-fillers) may prove to be a suitable solution for this concern. Using a 2 die-stack test vehicle with a bump pitch of 40 μm (with Cu and Cu/Sn bumps) and an underfill gap of 13.5 μm, four (4) different underfill materials (2 NUFs and 2 WAUFs) were screened. This paper will report on the assessment done for both wafer applied and no flow underfill materials, the differences in the application process, the materials filling and stacking process capabilities and finally the reliability of the 3D stacks. The materials were initially screened based on the test vehicle geometry then processed thru the different phases of the screening process. The changes in thermo-compression bonding parameters used in the experiment to improve the electrical yields will also be discussed. It will also be shown how underfill materials with and without fillers differ in the thermo-compression bonding force required to be able to get good bump-to-bump connection.

3D IC process development for enabling chip-on-chip and chip on wafer multi-stacking at assembly

Along with the flow and the fundamental focus on 3D integration, is the study in enabling stacking as well as assessing the needs to make it comparable to current manufacturing standards. To do this we take a look on key essential elements of a manufacturing line and applying it to the stacking process. Key areas of focus is process stability, control and ability to reducing the bond parameters (time, temp and force). With this we take a look at the developments done to enable such a condition and allowing the gathering and analysis of relevant data for enabling chip-on-chip (CoC) and chip-on-wafer (CoW) stacking in assembly production. CoC and CoW bonding is a stacking scheme in the 3D IC integration flow where diced top dies are bonded individually, using thermocompression bonding (TCB), directly over a whole bottom wafer or individual chips. These two methods have their advantages and disadvantages during assembly. One is to bond each chip only on another individual chips diced prior stacking, which is identified as CoC. Another is to place multiple chips in a single whole wafer then do the dicing afterwards. Both can be configured to adapt for multi-stacking. In this paper, we present the applicability of each process to actual production. We place side by side advantages and disadvantages for both methods with actual bond results. We also take a look on major parameters involved and innovative solutions used to address challenges. Coverage of this paper involves CoC and CoW stacking. Experiments are done on units using no-flow underfill (NUF) and wafer-level underfill (WLUF). The study covers learnings on the process development of die multi-stacking on 3D IC applications The paper will cover parameters, equipment and materials involved during the CoC and CoW bonding process. The goal of the paper is to show process development advances on 3D integration.

Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside

In 3D IC technology, temporary bonding systems and stacking/assembly process are identified as critical elements given all the concerns on wafer handling amidst BEOL processes and how to do the stacking as best as one could in so many different schemes. In between the temporary bonding systems and stacking/assembly process, is a group and series of processes that link the two. This is collectively and commonly known as the pre-assembly process. This paper presents the in-house pre-assembly 3D IC process flow for thinned wafer with micro-bumps on the backside along with the different challenges on materials and processes on each step. Most importantly, this paper reports on a solution found that enabled pre-assembly process to successfully provide a bridge from temporary bonding systems to stacking/assembly process: a UV dicing tape that can handle the complexities at hand when processing thinned 3D IC wafers with backside micro bumps in pre-assembly integration.

Wafer reconstruction: An alternative 3D integration process flow

Wafer reconstruction is a process of forming an integral handle-able wafer by filling the gaps between the dies after die-to-wafer assembly to allow for further processing on the landing wafer, e.g. thinning, redistribution layer deposition, and bumping. This paper examines key aspects and challenges of different wafer reconstruction process flows. Based on analytical and finite element method modeling, guidelines for material selection and structural design are generated. One selected process flow is successfully demonstrated in a typical 300 mm eWLB production environment, proving the feasibility of wafer reconstruction as a 3D integration process flow.

Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking

The demands and challenges in pushing the limits of Moores Law made the 3D IC stacking radiate the pressure for MPTs (materials, processes and tools) in keeping up with the technology. The 3D IC architecture design built around the TSVs, micro-bumps and thinned wafers/dies is the center of the show, of which the MPTs must conform and be viable to be part of the supporting cast. Underfillings main objectives is to provide the mechanical stability for micro-bumps and prevents moisture between the resulting gap between dies before the 3D stack is sent for packaging. With several complexities in 3D stacking had to be considered and addressed in applying the underfill materials. Complexities such as the stacking options Die-to-Die (D2D) or Die-to-Wafer (D2W), the thicknesses of the dies to be stacked (~50 um die thickness), the thermo-compression bonding parameters to be used and the behavior of the underfill materials to the different process parameters had to considered during the characterization process of underfills.

Microscrubbing: An alternative method for 3D thermocompression bonding CuCu bumps and high bump density devices with low force, time and temperature

Requirements for thermocompression bonding (TCB) successfully are dependent on the material as well as the area required to join. One of the paths for 3D integration is bonding Cu to Cu bumps or TSVs to bumps. A second path is by integrating fine pitch high density array of bumps, which may equate to >37000 bumps in a 8×8mm die size. Both require a significant amount of pressure as well as temperature before a good bond is achieve. For Cu to Cu bonding, temperatures >300°C is required as well as a compressive force that is needed to overcome the yield point of the metal, causing plastic deformation. On fine pitch high density array of bumps, a massive amount of force is needed to overcome the area of metal to bond. For instance a device with 37000 bumps (40μm pitch) would require at least 121kg of force to successfully bond. In this paper, we take a look on an alternative method of thermocompression bonding where we define, explore and characterize microscrubbing as an added process step during the bond. Experiments comparing differences between the standard TCB and the alternative method will also be explained. The experiment set involves die to die (D2D) stacking and is also applicable to D2W stacking. Experiments are done considering units with underfill using no-flow types. We discuss key understanding on the significant difference and improvements which microscrubbing contributes to the whole bonding process. It also touches on possible effects to bond quality and underfill reactions. In summary this paper covers tool parameters and material behavior during the thermocompression stacking process, exploring microscrubbing as an alternative method to direct TCB. The goal of the paper is to facilitate fundamental learnings and improvements on 3D stacking as a whole by exploring alternative methods.

3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement

This paper examines the key aspects for quality improvement and throughput enhancement of thermal compression bonding (TCB) process using dry film laminated wafer-level underfill (WLUF) material. The WLUF material must have good compatibility with pre-assembly and assembly process steps. And all the process steps after and including WLUF lamination have to be co-optimized to ensure the integrity of the WLUF material, consequently leading to higher stacking yield. Good bump joining and underfill filling quality is achieved by optimization different stages of the TCB profiles. A new method enabled by WULF, termed vertical collective bonding (VCB), is applied to multi-layer 3D stacking, producing good bonding quality and significant process time saving. Multi-layer 3D stacks made by the VCB process show good thermomechanical reliability in high temperature storage and thermal cycling tests.

Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials

With the emergence of 3D technology to answer the challenging limits of Moores Law, certain features in todays 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performance of the 3D package. Electrical tests on the daisy chain of the test vehicle and package robustness in terms delamination in the interfaces of the package were checked during the different reliability readouts.