Andy Miller

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Reflow process optimization for micro-bumps applications in 3D technology

In this paper a reflow process for fine-pitch micro-bumps is studied. A mathematical model for the reflow process is proposed and verified by experimental measurements. The influence of reflow profile parameters on the shape of micro-bumps, will be discussed using three commercial reflow ovens. Furthermore, measurement results of bump height variations after reflow over a 300mm wafer will be presented.

W2W permanent stacking for 3D system integration

In this paper, we present advances in 300mm wafer-to-wafer (W2W) oxide-oxide bonding for high density 3D interconnect application. A CMOS compatible low temperature oxide-oxide bonding method has been developed which yields consistent void-free bonding. In addition, sub-micron W2W alignment accuracy has been demonstrated with standalone test materials using an integrated permanent bonding platform.

3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects

In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.

Cobalt UBM for fine pitch microbump applications in 3DIC

In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer and single IMC (intermetallic compounds) and according to calculations using Cobalt as UBM can reduce consumption of UBM material by solder which is attractive for sub 10um pitches of microbumps. However, cobalt oxidizes very fast which results in poor wetting by solder as shown in Figure 1. This Figure shows two SEM images of cross section of 20um (left) and 50um (right) pitches microbumps from IMEC test vehicles where poor solder wetting is observed. It can be seen than in both cases Sn is deformed during TCB (thermo-compression bonding) bonding but due to oxide formation on cobalt bumps there is no reaction between Sn and Co. Such a joints may have weak electrical connection however, it is not suitable for a reliable device. Therefore surface treatment/passivation is required for cobalt bumps.

Development of multi-stack dielectric wafer bonding

We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.

Die to wafer 3D stacking for below 10um pitch microbumps

Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this paper.

Process development to enable die sorting and 3D IC stacking

3D stacking is a relative new technology and presents numerous challenges that need to be addressed for enabling high volume manufacturing. Yield and reliability are strongly affected by typical 3D processes: TSV, wafer thinning, stacking. For 3D stacking the die thickness is typically 50um with some exceptions for Interposer applications (typically 100um thick). This work describes some of the key challenges that need to be addressed to enable stacking of thick and thin dies. In this paper we report on process steps and equipment optimization that are required to enable 3D stacks. We focus on two main processes: die sorting (or die pick and place) and die stacking. For die sorting we report on the parameters considered to select the right ‘eject’ and ‘pick up’ tools and present considerations for process optimizations. For die stacking we report about temperature control during stacking and about the effects that foreign particles may have on stacking alignment.

High-bandwidth density optically interconnected terabit/s boards

Within the European Project TERABOARD, a photonic integration platforms including electronic-photonic integration is developed to demonstrate high bandwidth high-density modules and to demonstrate cost and energy cost target objectives. Large count high bandwidth density EO interfaces for onboard and intra-data center interconnection are reported. For onboard large count interconnections a novel concept based on optical-TSV interconnection platform with no intersections and no WDM multiplexing is reported. All input/output coupler arrays based on a pluggable silica platform are reported as well.

3D-SoC integration utilizing high accuracy wafer level bonding

This paper describes ultra-fine pitch 3D integration development using wafer level Cu/insulator hybrid bonding approach on 300mm substrate. Via-middle process with TSV dimension of 5×50μm is utilized to demonstrate and characterize vertical interconnects formed via face-to-face wafer-to-wafer (W2W) bonding. Key process steps are introduced with specific requirements and challenges. A non-SiO2 insulator is studied and chosen to enable a high mechanical bond strength with a low temperature anneal (≤250 °C). High alignment accuracy (< 400nm) is achieved with an advanced bonding system, which allows comprehensive characterizations of interconnect pitch scaling through various test structures. Finally, a high repeatability of the electrical performance of 3.6 μm pitch bonded structures is demonstrated statistically across numerous wafer pairs thanks to the precise Cu-Cu contacts established during bonding.