C. Gerets

Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs

Assembling multi-layer thinned Si chips to form 3D ICs in a fast, reliable, and cost-effective manner is one of the key processes to enable wider application and commercialization of 3D integration. In this paper the essential aspects of process development for stacking multi-layer 3D ICs are investigated. Combining thermo-compression bonding (TCB) process and the usage of pre-applied wafer-level underfill (WLUF) can significantly reduce the process complexity and time. A novel vertical collective bonding method is proposed and experimentally implemented, showing great potential in process improvement and throughput increase. Based on these techniques, stacking of multiple layers of 50 μm thick chips on bottom dies is successfully demonstrated. Daisy chains consisted of TSVs 5 μm in diameter and 20 μm pitch micro joints, in both bump-to-bump (Sn-to-Cu) and TSV-to-bump (Cu-to-Cu) bonding schemes, are connected with good electrical yield between all the stacked layers.

Wafer applied and no flow underfill screening for 3D stacks

As the demand for 3D packaging increases, selecting reliable and cost effective materials to be used to build these complex packages has gained a lot of importance. As current IC technology nodes are becoming “Moore-than-Moore” challenging, thus industry and research institutes alike are trying to find ways of addressing this challenge. The integration of new types of underfill materials in 3D stacking is one very important part of the package material set that will determine its reliability and cost effectiveness. With the introduction of 3D technology, bump sizes and pitches have been scaled down significantly which in turn has also shrank underfill gaps between dies which complicates the assembly of 3D stacks. The need of new underfill materials and underfilling concepts becomes inevitable. It is quite difficult to make traditional capillary type underfills and underfilling methods to work due to the very narrow gaps and fine bump pitches that 3D stacks have. Pre-applied underfills (Wafer Applied or No Flow) with or without fillers (submicron or Nano-fillers) may prove to be a suitable solution for this concern. Using a 2 die-stack test vehicle with a bump pitch of 40 μm (with Cu and Cu/Sn bumps) and an underfill gap of 13.5 μm, four (4) different underfill materials (2 NUFs and 2 WAUFs) were screened. This paper will report on the assessment done for both wafer applied and no flow underfill materials, the differences in the application process, the materials filling and stacking process capabilities and finally the reliability of the 3D stacks. The materials were initially screened based on the test vehicle geometry then processed thru the different phases of the screening process. The changes in thermo-compression bonding parameters used in the experiment to improve the electrical yields will also be discussed. It will also be shown how underfill materials with and without fillers differ in the thermo-compression bonding force required to be able to get good bump-to-bump connection.

Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

In this paper, we present a novel methodology using a thermal test chip to characterize the bulk thermal conductivity and the thermal contact resistance of underfill materials in die-die interfaces of 3D stacks for application-realistic test conditions. Since a silicon chip is used, the thermal properties can be extracted for the same material interfaces (finishing of the Si surface) and the same processing conditions (bonding and temperature profile during curing of the underfill material) as in the intended application. In the proposed methodology, transient thermal measurements obtained using a test chip with integrated heaters and sensors, are combined with thermal finite element simulations to extract the thermal properties. The proposed method is applied to extract the thermal properties and compare the thermal performance of 8 underfill materials. The materials are thermally characterized before and after curing. It is shown that the comparison of the temperature profiles before and after curing can indicate void formation or delamination during the curing stage.

3D stacking of Co- and Ni-based microbumps

In this paper,the wettability, quality of joint formation and electrical yield of daisy chains in 3D stacks when using Cobalt and Nickel as UBM with different finish layers such as immersion Au, ELD NiB, ELD Cu and SAM are investigated. The performance of the stacks are characterized by cross-section SEM images, EDS analysis and electrical resistance measurement of the daisy chains.

Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside

In 3D IC technology, temporary bonding systems and stacking/assembly process are identified as critical elements given all the concerns on wafer handling amidst BEOL processes and how to do the stacking as best as one could in so many different schemes. In between the temporary bonding systems and stacking/assembly process, is a group and series of processes that link the two. This is collectively and commonly known as the pre-assembly process. This paper presents the in-house pre-assembly 3D IC process flow for thinned wafer with micro-bumps on the backside along with the different challenges on materials and processes on each step. Most importantly, this paper reports on a solution found that enabled pre-assembly process to successfully provide a bridge from temporary bonding systems to stacking/assembly process: a UV dicing tape that can handle the complexities at hand when processing thinned 3D IC wafers with backside micro bumps in pre-assembly integration.

Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking

The demands and challenges in pushing the limits of Moores Law made the 3D IC stacking radiate the pressure for MPTs (materials, processes and tools) in keeping up with the technology. The 3D IC architecture design built around the TSVs, micro-bumps and thinned wafers/dies is the center of the show, of which the MPTs must conform and be viable to be part of the supporting cast. Underfillings main objectives is to provide the mechanical stability for micro-bumps and prevents moisture between the resulting gap between dies before the 3D stack is sent for packaging. With several complexities in 3D stacking had to be considered and addressed in applying the underfill materials. Complexities such as the stacking options Die-to-Die (D2D) or Die-to-Wafer (D2W), the thicknesses of the dies to be stacked (~50 um die thickness), the thermo-compression bonding parameters to be used and the behavior of the underfill materials to the different process parameters had to considered during the characterization process of underfills.

3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement

This paper examines the key aspects for quality improvement and throughput enhancement of thermal compression bonding (TCB) process using dry film laminated wafer-level underfill (WLUF) material. The WLUF material must have good compatibility with pre-assembly and assembly process steps. And all the process steps after and including WLUF lamination have to be co-optimized to ensure the integrity of the WLUF material, consequently leading to higher stacking yield. Good bump joining and underfill filling quality is achieved by optimization different stages of the TCB profiles. A new method enabled by WULF, termed vertical collective bonding (VCB), is applied to multi-layer 3D stacking, producing good bonding quality and significant process time saving. Multi-layer 3D stacks made by the VCB process show good thermomechanical reliability in high temperature storage and thermal cycling tests.

Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials

With the emergence of 3D technology to answer the challenging limits of Moores Law, certain features in todays 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performance of the 3D package. Electrical tests on the daisy chain of the test vehicle and package robustness in terms delamination in the interfaces of the package were checked during the different reliability readouts.

Thermal compression bonding of 20 μm pitch micro bumps with pre-applied underfill — Process and reliability

Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted inter-metallic compound (IMC) layer in the joints. Electrical measurement of the daisy chains on the as-bonded chips does not reveal any significant difference between the samples made with different bonding forces. The reliability of the two types of joints were further studied in two post-bonding tests, namely the resistance measurement of daisy chains at an elevated temperature and stack-level thermo-cycling test. Both tests show a better reliability performance from the bump joints with less underfill entrapment and completely reacted IMC layer.

Surface Treatment to Enable Low Temperature and Pressure Copper Direct Bonding

One of the major area of interest of the electronics packaging industry is the formation of interconnects between the chips in a 3D package. Copper has been proven to be a suitable candidate for the conductive material in back-end-of-line due to its low electrical resistivity and high electro-migration resistance. Due to this favorable property of copper, it is also used to form microbumps and through silicon vias (TSVs) for 3D stacking. To stack known good dies (KGDs), die-to-die (D2D) and die-to-wafer (D2W) bonding are the traditional approaches used in 3D stacking. Flip chip thermo-compression bonding (TCB) is employed to enable a joint formation between the microbumps of the top chip and the bottom substrate. Most TCB tools are limited by pressure and temperature parameters. High temperature and pressure requirements make the bonding process costly and may cause additional reliability concerns. Good joint formation at low temperature and low pressure is preferred to address these issues for various applications. The aim of this paper is to explore different dry and wet cleaning approach to understand its effect on the copper surface and its effect to enable low temperature (250 °C) and low pressure (~23 MPa) bonding in a cleanroom environment without compromising the joint quality.