Alessandro Bosi

An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR

A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic.

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-

A 0.076 mm2 12b 28 nm 600 MS/s 4-way time interleaved ADC with on chip buffer is presented. The usage of a subranging scheme consisting of a coarse SAR ADC followed by an incremental ΔΣ fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The ADC area has been optimized by using a segmented charge-sharing charge-redistribution DAC. The prototype achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming 26 mW.

\Delta \Sigma

An example of usage of ADC hybrid techniques and DAC segmented topologies to achieve high power efficiency and low total area is presented. The resulting hybrid ADC architecture consisting of a coarse SAR ADC followed by an incremental ΔΣ fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The usage of a segmented charge-sharing charge-redistribution DAC scheme enables significant area saving compared to conventional DAC topologies. The 28 nm 600 MS/s four-way interleaved prototype ADC achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming only 26 mW for a total area of 0.076 mm2.

ADC With On-Chip Buffer in 28 nm CMOS

Integration of low-power and area-efficient ADCs is a key differentiator in modern mixed-signal SoCs. In scaled technologies, power challenges have been addressed using SAR architectures, often in combination with techniques like redundancy, asynchronous operation, and time interleaving to meet the application sampling rate requirements. However, for high-resolution ADCs (9b+ ENOB), a traditional SAR is intrinsically energy-inefficient since it reuses the same low-noise comparator to perform both coarse conversions (where little accuracy is needed) and fine conversions (where thermal noise is of paramount importance). This is addressed in [1,2] with hybrid SAR-pipeline architectures that employ SAR as subADCs, but whose noise performance is determined by a high-efficiency interstage amplifier as opposed to the comparator.

Hybrid and Segmented ADC Techniques to Optimize Power Efficiency and Area: The Case of a 0.076 mm 2 600 MS/s 12b SAR-ΔΣ ADC

VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below −65dBc to fully exploit 15b-per-tone bit loading [1].