V. Vidojkovic

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

A digitally modulated 60GHz polar transmitter in 40nm CMOS

A 60GHz polar Tx prototype implemented in 40nm CMOS includes a two-stage PA with an RF-DAC, an I-Q upconversion mixer, a 60GHz LO hybrid and a digital synchronization interface. Saturated output power is approx. 10dBm, while RF output and baseband input bandwidths are 9GHz and 1.2GHz, respectively. The linear RF-DAC resolution is 5 bits. EVM degradation and spectral mask out-of-band distortion appear at input powers higher than 6dB above P-1dB. EVM is -19dB and -16dB at full rate, and -25.5dB and -22dB at reduced rates for QPSK and 16-QAM signals, respectively. The Tx consumes 75mW from 0.9V, and the core occupies 0.18mm2 of the 2.38mm2 testchip.

A 52–66GHz subharmonically injection-locked quadrature oscillator with 10GHz locking range in 40nm LP CMOS

A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. A large locking range (10GHz), tunable over the 52-66GHz band, is achieved using transformer-coupled resonators. A simple calibration scheme is proposed that only relies on a relative power measurement of the oscillator output signal. The wide locking range, the wide tunability and the simple calibration scheme make this injection-locked quadrature oscillator design suitable for frequency synthesis in mm-wave CMOS communication systems.

A 40 nm LP CMOS PLL for high-speed mm-wave communication

A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63–70 GHz and 72–81 GHz frequency bands. It achieves −85 dBc/Hz in-band phase noise at 64 GHz, corresponding to −19.4 dBc integrated phase noise, while consuming 60 mA from a 1.1 V supply.

CMOS low-power transceivers for 60GHz multi Gbit/s communications

The availability of 9GHz bandwidth around 60GHz in combination with simple modulations schemes, low-cost radio ICs and small antenna size, allows for multi Gbit/s wireless communications. In this article the potential of 60GHz wireless communications is evaluated from system, application and user point of view. Further, design challenges for 60GHz CMOS transceivers are identified. State-of-the-art designs show that short-range high-datarate radio links based on CMOS ICs can be made, potentially helped with beamforming.

A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS

A polar TX based on a 10GSample/s RF-DAC aimed at 802.11ad applications realizes more than 30dB alias attenuation and exceeds 3GHz input bandwidth with 6x oversampling factor. The PA drain efficiency is 29.8% with a Psat of 10.8dBm. Average TX output power is 5.3dBm with 15.3% PA efficiency running QPSK at 3.3Gb/s datarate and -23.6dB EVM. Corresponding 16-QAM values are: 3.6dBm with 11.6% at 6.7Gb/s and -18.1dB EVM. The 0.18mm2 TX core in 40nm bulk-CMOS consumes 40.2mW from 0.9V.

A 6.6 mW inductorless static 2:1 frequency divider operating up to 60 GHz in 28 nm CMOS

This paper presents an inductorless static 2:1 frequency divider operating up to 60 GHz. In order to save the chip area no peaking inductors are used in this design. Alternatively, to achieve the high operating frequency, the range is extended by asymmetrical sizing of the data and latch transistors and by reducing the load of the following buffer stage. The load reduction is achieved by means of a gate-drain capacitance neutralization in the following differential buffer stage. The circuit is realized in a 28 nm CMOS technology. Measurements show that the divider exhibits a maximum operating frequency of 60 GHz and features an input sensitivity below 0 dBm over a broad input frequency range of 34 GHz. The divider core consumes 7.3 mA from a single 0.9 V supply.