Srinivas Gandikota

Planarization of Copper Thin Films by Electropolishing in Phosphoric Acid for ULSI Applications

Electropolishing of thin films poses additional challenges in comparison to hulk material polishing. The existence of a resistive anode/electrolyte boundary layer is crucial for achieving polishing. A finite amount of copper is required to he anodically dissolved to create the boundary layer of the appropriate thickness for effective electropolishing of a given hillock. This is a significant consideration in the application of electropolishing for planarization of thin films where the disparity in the topography is significant in proportion to the thickness of the film. Here electropolishing is shown to effectively remove the bulk of electrodeposited copper layers used in ultralarge scale integration (ULSI) metallization schemes without application of mechanical force and to planarize local topography. Efficient polishing can be achieved under galvanostatic conditions (i.e., constant current between the wafer and a counter electrode). Anodic transient studies indicated that the mechanism of formation of the boundary layer (in mass-transport controlled regime) is determined by the diffusive transport of an acceptor species to the anode/electrolyte Interface. Effects of changes in current density and rotational speed of wafer on the extent of planarization have heen determined. Under optimal galvanostatic and hydrodynamic conditions, the disparity in the topography over wide trenches adjacent to dense features decreased by 60%.

Adhesion studies of CVD copper metallization

Abstract The adhesion of chemical vapor deposition (CVD) Cu thin films to various barriers was observed to improve with a post-deposition anneal or a physical vapor deposition (PVD) Cu flash layer on the barrier before depositing CVD Cu. The ambient exposure of the barrier before the deposition of CVD Cu has been observed to lead to degradation of adhesion in both CVD Cu seed and CVD/PVD Cu high vacuum integrated metallization schemes. The integrated CVD and PVD Cu deposition scheme exhibits better adhesion due to the inherent annealing provided during the PVD deposition which is carried out at temperatures between 300 and 400°C. We have evaluated both qualitative and quantitative tests — tape test, Stud pull test and 4-point bend test — in understanding adhesion and observed that each of these tests give different details of interface breakdown.

Electrodeposition of copper–tin alloy thin films for microelectronic applications

The continuing shrink in device size has generated great interest to create interconnects with low resistivity and superior resistance to electromigration (EM) and stress migration (SM) in comparison to the existing Al or Al-alloy interconnections. Copper has become the metal of choice to meet the needs of present and future generation devices. In order to improve the intrinsic resistance of copper to EM/SM induced failure, alloying elements can be added into copper metallurgy. In the present investigation, we discuss a method to co-deposit an alloy of copper and tin in sub-microscopic features with high aspect ratio using a sulfate bath. It is observed that a small amount tin begins to co-deposit at potentials smaller than the equilibrium reduction potential. Under activation control regime, the composition is not affected by current density. The results of this study conclude that substantial tin deposition occurs upon onset of mass-transport limitation. It is found that a finite amount of time is required before electrolysis is controlled by mass-transfer. The transition time and hence, the composition of the plated film is affected by the hydrodynamic conditions, current density, and electrolyte composition. These factors must be taken into account in order to control the composition profile of tin in vias and trenches.

Chemical studies of CVD Cu deposited on Ta and TaN barriers under various process conditions

Contamination in the matrix of CVD copper films and at the interface between CVD copper films and barrier layers has been characterized using XPS, SIMS, XRD and RGA. Contamination in the CVD copper matrix has been found to increase with increasing precursor flow rate and with decreasing wafer temperature. Interfacial contamination has been investigated in an attempt to quantitatively define acceptable levels of contamination and ultimately reduce the effect of these contaminants on the integrated film stack. Sputtered copper flash layers for CVD copper deposition are also shown as highly effective for reducing the levels and effects of incorporated contamination.

High-k/metal gate stacks in gate first and replacement gate schemes

In this work, representative high-k/metal gate MOS-capacitor stacks were fabricated in both gate first and replacement gate integration schemes. Aluminum- and lanthanum- based cap layers (both widely accepted as Vt tuning cap layers in the industry), in addition to TiN metal gate, can tune the effective workfunction towards PMOS and NMOS, respectively. Varying Ti:N stoichiometry in TiN can induce >250mV change in TiN workfunction. 1 volt separation between NMOS and PMOS was achieved by screening various workfunction materials in replacement gate scheme. Substrate modification during the growth of aluminum was key to achieving void-free aluminum gap fill in narrow gate trenches.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Advantage of Siconi Preclean over Wet Clean for Pre Salicide Applications Beyond 65nm Node

For advanced devices at 65 nm node and beyond, nickel silicide formed by depositing Ni or its alloys with subsequent annealing has been chosen as the source/drain and gate contact materials. An in-situ dry chemical cleaning technology (Siconi ) has been developed to be integrated with PVD nickel deposition, thus forming a defect-free silicide/Si interface. Queue time related surface contamination and defects caused by using wet (HF) chemical cleaning are thus eliminated. The dry and wet etch methods are compared in this paper in terms of the film Rs, microstructure and thermal stability, as well as the line width effects measured on test wafers.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Novel metal gates for high κ applications

The development of gate systems suitable for high κ dielectrics is critical to the advancement of complementary metal-oxide-semiconductor (CMOS) devices. Both the effective work function and material stability are key parameters to these systems. A systematic study of metal gates of the composition HfxSi1-x (0.25 ≤ x ≤ 1) is demonstrated here, including XPS, XRD and four point probe measurements. The effective work function of each material is evaluated and it is shown that it can be tuned from 4.5 to less than 4.0 eV. Suitable work functions for n-channel metal-oxide-semiconductor applications (4.05 ± 0.2 eV) were achieved using hafnium rich compositions; however, XPS and diffraction measurements confirmed that these materials demonstrated a high propensity to oxidise, causing the reduction of the underlying oxides, making them unsuitable for commercial application.

Enhancing the electromigration resistance of copper interconnects

Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers show that atomic layer chemical vapor deposited (ALCVD) barrier and/or metallic cap layers are key to realize structures with superior EM lifetimes.