Deenesh Padhi

Planarization of Copper Thin Films by Electropolishing in Phosphoric Acid for ULSI Applications

Electropolishing of thin films poses additional challenges in comparison to hulk material polishing. The existence of a resistive anode/electrolyte boundary layer is crucial for achieving polishing. A finite amount of copper is required to he anodically dissolved to create the boundary layer of the appropriate thickness for effective electropolishing of a given hillock. This is a significant consideration in the application of electropolishing for planarization of thin films where the disparity in the topography is significant in proportion to the thickness of the film. Here electropolishing is shown to effectively remove the bulk of electrodeposited copper layers used in ultralarge scale integration (ULSI) metallization schemes without application of mechanical force and to planarize local topography. Efficient polishing can be achieved under galvanostatic conditions (i.e., constant current between the wafer and a counter electrode). Anodic transient studies indicated that the mechanism of formation of the boundary layer (in mass-transport controlled regime) is determined by the diffusive transport of an acceptor species to the anode/electrolyte Interface. Effects of changes in current density and rotational speed of wafer on the extent of planarization have heen determined. Under optimal galvanostatic and hydrodynamic conditions, the disparity in the topography over wide trenches adjacent to dense features decreased by 60%.

Electrodeposition of copper–tin alloy thin films for microelectronic applications

The continuing shrink in device size has generated great interest to create interconnects with low resistivity and superior resistance to electromigration (EM) and stress migration (SM) in comparison to the existing Al or Al-alloy interconnections. Copper has become the metal of choice to meet the needs of present and future generation devices. In order to improve the intrinsic resistance of copper to EM/SM induced failure, alloying elements can be added into copper metallurgy. In the present investigation, we discuss a method to co-deposit an alloy of copper and tin in sub-microscopic features with high aspect ratio using a sulfate bath. It is observed that a small amount tin begins to co-deposit at potentials smaller than the equilibrium reduction potential. Under activation control regime, the composition is not affected by current density. The results of this study conclude that substantial tin deposition occurs upon onset of mass-transport limitation. It is found that a finite amount of time is required before electrolysis is controlled by mass-transfer. The transition time and hence, the composition of the plated film is affected by the hydrodynamic conditions, current density, and electrolyte composition. These factors must be taken into account in order to control the composition profile of tin in vias and trenches.

Effect of electron flow direction on model parameters of electromigration-induced failure of copper interconnects

This investigation studies the effects of the direction of electron flow on the activation energy and current exponent of electromigration failure of copper interconnects using conductors terminated by vias at both ends. The activation energy of a downstream case (0.91 eV) was found to be similar to that of an upstream case (0.86 eV), suggesting that failure was primarily caused by diffusion along the Cu/SiNx interface for both cases. Mean time to fail with the upstream flow condition exceeded that with the downstream condition by a factor of ∼2 at 300 °C and 1(106) A/cm2. The current exponent (with a link current density in the range of 1×106 to ∼5×106 A/cm2) of a 0.22 μm via/link structure was determined to be 1.44 and 1.87 with upstream and downstream electron flow, respectively. These differences have been correlated to the locations of void nucleation and their physical size for the two electron flow conditions. Furthermore, increasing the via/link size resulted in a slight increase in the current exponent, consistent with the model proposed by Lloyd [J. R. Lloyd, J. Appl. Phys. 69, 7601 (1991).]This investigation studies the effects of the direction of electron flow on the activation energy and current exponent of electromigration failure of copper interconnects using conductors terminated by vias at both ends. The activation energy of a downstream case (0.91 eV) was found to be similar to that of an upstream case (0.86 eV), suggesting that failure was primarily caused by diffusion along the Cu/SiNx interface for both cases. Mean time to fail with the upstream flow condition exceeded that with the downstream condition by a factor of ∼2 at 300 °C and 1(106) A/cm2. The current exponent (with a link current density in the range of 1×106 to ∼5×106 A/cm2) of a 0.22 μm via/link structure was determined to be 1.44 and 1.87 with upstream and downstream electron flow, respectively. These differences have been correlated to the locations of void nucleation and their physical size for the two electron flow conditions. Furthermore, increasing the via/link size resulted in a slight increase in the current e...

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

Defect gallery and bump defect reduction in the self Aligned Double Patterning module

The Self Aligned Double Patterning (SADP) module is one scheme to form 3X or 2X line structures by using a dry scanner or immersion scanner. After reliable processes are developed, defect data collection, understanding, characterization, and reduction become important. The learning we obtained at the Mayden Technology Center at Applied Materials reduced ramp time at our customer sites and provided new directions to improve our processes. In this paper, the defect type and evaluation per process to the final 3X or 2X structures in SADP flow are discussed. An in-depth study of the impact of bump defects, bump formation, and a potential solution involving an improved film deposition process are presented.

Wafer edge polishing process for defect reduction during immersion lithography

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

Enhancing the electromigration resistance of copper interconnects

Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers show that atomic layer chemical vapor deposited (ALCVD) barrier and/or metallic cap layers are key to realize structures with superior EM lifetimes.

300mm copper low-k integration and reliability for 90 and 65 nm nodes

The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.

Influence of plating parameters on reliability of copper metallization

This work investigates the impact of plating parameters on the physical and electrical properties of plated copper films. Process parameters such as the plating current density and wafer rotation speed are known to affect the grain size and the residual stress in plated Cu films. We correlate the process parameters with trapped contamination in the films, which in turn influences the pre/post-anneal grain size and the relaxation of the residual stress. Preliminary reliability measurements show that the longevity of the interconnect structure is dependent on the intrinsic properties of the plated copper.

Characterization of electroless copper as a seed layer for sub-0.1 /spl mu/m interconnects

Complete gapfill of 0.1 /spl mu/m features with electroless Cu seed layers and electroplated Cu was demonstrated. Electrical tests on test structures indicated similar line and via chain resistance, yield and line-to-line leakage current on wafers with electroless Cu seed and PVD Cu seed layers filled with electroplated Cu.