Alessandro Pezzotta

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fabricated in a commercial 28 nm bulk CMOS process with the perspective of using it for the future silicon-based detectors. The DC electrical behavior of nMOSFETs is studied up to 1 Grad TID. All tested devices demonstrate to withstand that dose without any radiation-hard layout techniques. In spite of that, they experience a significant drain leakage current increase which may affect normal device operation. In addition, a moderate threshold voltage shift and subthreshold slope degradation is observed. These phenomena have been linked to radiation-induced effects like interface and switching oxide traps, together with parasitic side-wall transistors.

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs.

Nanoscale MOSFET modeling for the design of low-power analog and RF circuits

This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient is then presented as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation. It is then used to describe the basic trade-offs faced in the design of single-stage amplifiers between bias current and transconductance, gain-bandwidth and thermal noise. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are then presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design and can be used as design guidelines for optimizing a design. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of commercial 40-nm and 28-nm bulk CMOS processes and with simulations using the BSIM6 model.

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage V^G-V^T0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency G^m/I^D, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G^ds/I^D follows a similar dependence with IC than the normalized G^m/I^D characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured I^D-V^G and I^D-V^D characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.

Total ionizing dose effects on analog performance of 28 nm bulk MOSFETs

This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few parameters, both the simplified large- and small-signal models present an excellent match with measurements at all levels of TID. The impacts of TID on essential parameters, including the drain leakage current, the threshold voltage, the slope factor, and the specific current, are then evaluated. Finally, TID effects on the transconductance Gm, the output conductance Gds, the intrinsic gain Gm/Gds and the transconductance efficiency Gm/Id are investigated.

Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

In this paper, a comprehensive charge-based predictive model of interface and oxide trapped charges in undoped symmetric long-channel double-gate MOSFETs is developed. The model involves essentially no fitting parameters, but first-principle calculations of both oxide and Si/oxide interface trapping. This charge-based approach represents an essential step toward compact modeling of ionizing dose and aging effects in advanced field effect devices. The soundness of this approach is confirmed by extensive comparisons with numerical TCAD simulations, while the analytical formulation helps understanding the most relevant parameters of the phenomena with respect to a specific technology. The model confirms its validity for all regions of operation, i.e., from deep depletion to strong inversion and from linear to saturation.

Linear analysis of phase noise in LC oscillators in deep submicron CMOS technologies

This paper investigates the phase noise in LC oscillators with NMOS cross-coupled pair by means of a linear analysis. The latter includes the impact of noise sources that are often neglected, such as gate leakage shot noise, induced gate noise and all terminal access resistances noise. Despite not considering up-conversion of flicker noise, this linear analysis still provides reliable and useful results, demonstrated by means of a detailed comparison between the analytical description and simulations results from a 40nm and a 28nm CMOS technology.

Total Ionizing Dose effects on a 28 nm Hi-K metal-gate CMOS technology up to 1 Grad

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. For nMOSFETs, the leakage current shows an increase of 2–3 orders of magnitude, while only moderate degradation for other parameters has been observed. For pMOSFETs, a more severe degradation of parameters has been measured, especially in the drain current. This work is relevant as the evaluation of a new generation of CMOS technologies to be used in future HEP experiments.

Nanoscale MOSFET Modeling: Part 2: Using the Inversion Coefficient as the Primary Design Parameter

This article illustrates the use of the inversion coefficient (IC) as the main design parameter to explore the various tradeoffs faced in the design of analog circuits. We start with showing that the same transconductance, gain-bandwidth (GBW) product, or input-referred thermal noise resistance of a common-source (CS) amplifier can be achieved with lower current by shifting the IC toward moderate inversion (MI) at the cost of a slight increase of the transistor aspect ratio and area. In such case the self-loading gate capacitance cannot be ignored, and accounting for it introduces a minimum bias current at an IC that lies in the middle of the MI to achieve a given GBW.