Goichi Yokomizo

A Parallel and Accelerated Circuit Simulator with Precise Accuracy

We have developed a highly parallel and accelerated circuit simulator which produces precise results for large scale simulation. We incorporated multithreading in both the model and matrix calculations to achieve not only a factor of 10 acceleration compared to the de facto standard circuit simulator used worldwide, but also equal or exceed the performance of timing-based event-driven simulators with the accuracy which matches that of SPICE-based circuit simulation. For example, a 89K element DRAM CAS circuit simulation can be performed in under 38 minutes with timing accuracy error as little as 7 ps.

A fast and accurate method of redesigning analog subcircuits for technology scaling

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to an MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods.

A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 h, making this method 5 times more efficient than conventional methods.

A new circuit recognition and reduction method for pattern based circuit simulation

A novel circuit recognition and reduction method to extract subcircuit data corresponding to the critical paths, including all relevant parasitics and internal loading, is presented. Circuit elements extracted from layout pattern data are combined to reconstruct logic gates, and a structure of the gates is recognized by the connection between the gate terminals. The recognized circuit data is reduced by tracing signal flows and picking up the gates along the specified critical paths. The circuit elements connected between a remaining net and an eliminated net are terminated as capacitive loads, and parasitic elements are merged or eliminated when the estimated error is permissible, compared with the specified error tolerance. The error is estimated by the first-order moment of the impulse response. Results on logic macrocells and memory peripheral control circuits show that the reduced circuit sizes are 15-50 times smaller, resulting in circuit simulation speedups of 50-300 times faster.<<ETX>>

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

A mixed-mode simulator is described that can simulate voltage fluctuations in the power supply network. Current flow due to logic events is taken into account in order to predict the voltage fluctuations. The difference between the maximum voltage fluctuations calculated by the proposed mixed-mode simulation and these calculated by conventional circuit simulation are within 20%, and we demonstrated the feasibility of the proposed simulation by simulating an entire MOS memory chip (36,000 transistors) in 75 minutes on an HP9000/735.