Masato Iwabuchi

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<<ETX>>

A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early floorplanning are performed. In this stage, logic contents are not known, but global structure of power/ground and clock networks, function partitioning and early floorplan give reasonable accuracy for global optimization of the chip. A case study shows the power voltage drop and critical path delay slowdown due to dynamic power voltage drop for a mixed analog-digital chip, and a good match with actual measurements is achieved.

A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates

An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing /spl alpha/-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.5/spl times/2 /spl mu/m/sup 2/ and the chip size is 11/spl times/11 mm/sup 2/. >

Logic-in-memory VLSI for mainframe computers

A bipolar 6Kb memory VLSI with 770 logic gates developed for virtual address translation and buffer storage control will be described. Access time and power dissipation are 6.7ns and 5.2W.

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

A mixed-mode simulator is described that can simulate voltage fluctuations in the power supply network. Current flow due to logic events is taken into account in order to predict the voltage fluctuations. The difference between the maximum voltage fluctuations calculated by the proposed mixed-mode simulation and these calculated by conventional circuit simulation are within 20%, and we demonstrated the feasibility of the proposed simulation by simulating an entire MOS memory chip (36,000 transistors) in 75 minutes on an HP9000/735.

Technology improvement for high speed ECL RAMs

The trends in high speed ECL random access memories (RAMs) are reviewed with emphasis on memory cell improvements for achieving high speed performance. State-of-the-art technologies including bipolar, BICMOS, memory-with-logic modules and logic-in-memory LSIs are discussed. Finally, some prospects for ultra-high speed RAMs are proposed.