Mikako Miyama

Pre-silicon parameter generation methodology using BSIM3 for circuit performance-oriented device optimization

We present a physical parameter extraction methodology for BSIM3v3 to generate accurate pre-silicon parameters (parameters created before device fabrication). Using this method, the parameters of the 0.20-/spl mu/m process device can be generated from a 0.25-/spl mu/m technology with 5% accuracy in a few minutes. We applied this method in optimizing the devices of our microprocessor in the early stages of design.

Statistical BSIM3 model parameter extraction and fast/slow model parameter determination for high speed SRAM parametric yield estimation

To achieve high yield without degrading performance, it is important to consider process variations during circuit designing. There is also a strong need of good model parameters for fast/slow cases, which represent the performance variations. We have developed a statistical model parameter extraction method, to extract sets of process related BSIM3 parameters from in-line measurement data such as drain saturation current and threshold voltage. This extraction method is based on our pre-silicon parameter generation methodology, which makes the model parameter predictable when changing some parameters related to the process. We have also proposed a method to determine the fast/slow model parameters using the statistical model parameters, for circuit designing. We have applied this method to a 0.20 /spl mu/m process SRAM test chip, and have obtained good results comparing to measurement, thus making it possible to estimate parametric yield by simulation.

A new circuit recognition and reduction method for pattern based circuit simulation

A novel circuit recognition and reduction method to extract subcircuit data corresponding to the critical paths, including all relevant parasitics and internal loading, is presented. Circuit elements extracted from layout pattern data are combined to reconstruct logic gates, and a structure of the gates is recognized by the connection between the gate terminals. The recognized circuit data is reduced by tracing signal flows and picking up the gates along the specified critical paths. The circuit elements connected between a remaining net and an eliminated net are terminated as capacitive loads, and parasitic elements are merged or eliminated when the estimated error is permissible, compared with the specified error tolerance. The error is estimated by the first-order moment of the impulse response. Results on logic macrocells and memory peripheral control circuits show that the reduced circuit sizes are 15-50 times smaller, resulting in circuit simulation speedups of 50-300 times faster.<<ETX>>

Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design

We present a physical parameter extraction methodology for BSIM3 to generate accurate pre-silicon parameters (parameters created before device fabrication). Using this method, the parameters of the 0.20 /spl mu/m process device can be generated from a 0.25 /spl mu/m technology with 5% accuracy in a few minutes. We applied this method in optimizing the devices of our microprocessor in the early stages of design.

Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.

Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters

We propose a circuit performance oriented device optimization methodology using pre-silicon parameters and critical paths which represent the performance of the chip. Based on our methodology, we successfully reduced the power consumption by 90% and, at the same time, increased the frequency by 30% from the initial design. The key to this optimization methodology is the pre-silicon parameter generation method, which can predict the device performance within 5% accuracy in a few minutes.

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

A mixed-mode simulator is described that can simulate voltage fluctuations in the power supply network. Current flow due to logic events is taken into account in order to predict the voltage fluctuations. The difference between the maximum voltage fluctuations calculated by the proposed mixed-mode simulation and these calculated by conventional circuit simulation are within 20%, and we demonstrated the feasibility of the proposed simulation by simulating an entire MOS memory chip (36,000 transistors) in 75 minutes on an HP9000/735.