Gordon Arthur Kelley

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. >

A 50 ns 16 Mb DRAM with a 10 ns data rate

A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described. It incorporates an architecture that supports either 11/11 or 12/10 RAS/CAS (row-address strobe/column-address-strobe) addressing. It is segmented to utilize bit redundancy of 2 lines/137-b lines/half quadrant, and separate word-redundant array of 24 lines/quadrant, providing any-for-any-word-line replacement within a quadrant. It has single-error-correct/double-error-detect (SEC/DED) error checking and correcting (ECC) Hamming odd-weight code/quadrant and either 5-V or 3-V operation. The design provides a RAS access of 50 ns with 16-ns fast-page access, 18-ns static column or toggle of 10 ns at 2.9 V and 85 degrees C. DRAM features are summarized.<<ETX>>