Erik L. Hedberg

SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off

In 65nm and smaller technologies, Vmin fails account for a substantial portion of the total fails seen in memories. Redundancy has traditionally been used to fix random point defects which can be modeled with Critical Area Analysis. As technologies migrate from 90 nm to 65nm, cost optimization requires consideration of Vmin yield fallout as well as random defects when selecting a SRAM memory redundancy scheme. Since added redundancy requires additional silicon area, redundancy schemes need to be balanced against the cost required to enable memory repairs.

Multipurpose DRAM architecture for optimal power, performance, and product flexibility

An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3 .34 or 5.04 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1 Mb x 16 operation with 2Mb x 8, 4Mb x 4, and 4Mb x 4 with any 4Mb independently selectable (4Mb x 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.

Line centering yield optimization

Sensitivity to local density effects in both products and scribe line macros is increasing in newer technologies. This can result in significant yield loss at product test because the product measurement structures do not match manufacturing scribe line disposition expectations. A novel strategy to mitigate this problem has been developed and implemented on 32nm IBM ASIC products. Conventional scribe line macro measurements are combined with measurement of macros in each product chip and measurement of the same macros in the scribe line. Four performance screen ring oscillators (PSROs) macros and 28 smaller ring oscillator macros are included in the design of each product. Identical product-like structures are inserted in the scribe line area. Measurements of the macros in the product are compared to the same macros in the scribe line. Measurement differences can be correlated to conventional scribe line macros. This information is used to qualify library elements used in a design system and to center manufacturing lines to optimize yield.