Keng L. Wong

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 /spl mu/m BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55/spl deg/C. >

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Traditional inaccuracies during manufacturing test of the thermal sensor circuit require excessive guard-bands. These guard-bands increase the chance of unnecessary microprocessor throttling and could introduce a less-than optimum power and thermal design envelope. Circuit techniques that minimize these errors are discussed, including an improved temperature-independent voltage pump, a remote thermal sensing scheme for hot-spot to sensor offset reduction, and a self-heating error calibration method. Experimental data obtained on a high performance 65nm Intel® Pentium® 4 microprocessor demonstrates the feasibility and effectiveness of these techniques, providing a combined potential accuracy improvement of up to 17°C.

A high performance 0.35-/spl mu/m 3.3-V BiCMOS technology optimized for product porting from a 0.6-/spl mu/m 3.3-V BiCMOS technology

A 0.35-/spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-/spl mu/m 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-/spl mu/m 3.3-V BiCMOS design to a 0.35-/spl mu/m design is described. The silicon results are described.

Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS

A novel self-biased PLL design incorporating a low-gain interpolated inverter-based ring oscillator VCO accomplishes several improvements for general purpose clock generation, namely lower bandwidth and lower short and medium-term accumulation jitter due to thermal noise and reference clock noise, while not sacrificing PSRR, area, and PVT insensitivity. Charge pump programmability provides an effective mechanism for bandwidth adjustments without requiring large circuit duplicates. Data collected on a high-k, metal gate 45 nm process confirms the suitability of the proposed scheme.

150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 /spl mu/m BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55/spl deg/C. >